Share the summary of MSP430F5529 clock module

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I started to learn a new CPU of MSP430 series, F5529. According to the method of learning 430 before, I began to understand its clock part. I learned it by referring to TI official routines. There was a program that confused me for a long time in the laboratory. This comment is as follows: ACLK=n/a, MCLK=SMCLK=BRCLK=default DCO=1.048576 MHZ As we all know, the clock system of msp430 is flexible and changeable. Its USC module has three clocks (MCLK, SMCLK, ACLK) and five clock sources (XT1CLK, VLO, REFOCLK, DCO, XT2) After PUC, the default configuration of UCS module is as follows: 1. XTI is in LF mode, as the clock source of XT1CLK. XT1CLK is used as ACLK. 2. DCOCLKDIV is used as MCLK 3. DCOCLKDIV is used as SMCLK 4. FLL module is enabled, XTI is used as FLL reference clock FLLREFCLK 5. XIN, XOUT pins are general I/O 6. XT2IN, XT2OUT pins are general I/O What confuses me is the second half of the sentence, MCLK=SMCLK=BRCLK=defaultDCO=1.048576 MHZ First of all, I am not sure where 1.045M comes from. Later, I found the relevant explanation in the Family User's Guide of the 5/6 series. As previously stated, FLL operation with XT1 is selected by default. If the crystal pins (XIN, XOUT)are shared with general-purpose I/Os, XT1 will remain disabled until the PSEL bits associatedwith the crystal pins are set. If XIN and XOUT are not shared with general-purpose I/O, XT1 is enabled. When a 32,768 Hz crystal is used forXT1CLK, the fault control logic immediately causes ACLK to be sourced by the REFOCLK, because XT1 is not stable immediately (see Section5.2.12). Once crystal startup is obtained and settled, the FLL stabilizes MCLK and SMCLK to1.048576 MHz and fDCO = 2.097152 MHz. The first half of this paragraph explains the default state of FLL and XT1 after power-up. The key is in the latter sentence, which says that when a crystal oscillator is started up, ACLK will be taken from an external 32.768KHZ crystal oscillator, and FLL will stabilize MCLK and SMCLK to 1.048576M and fDCO = 2.097152 MHz. I think 1.048576M should be taken from this place, but fDCO here = 2.097152 MHz. It is not much more than twice of 1.048576M, so why does it say MCLK=SMCLK=BRCLK=default DCO=1.048576 MHZ? So I pasted this sentence to Baidu, and found that most of them were copied from TI's official routines, and I didn't pay much attention to the comments. After my own exploration, I found that it is actually like this; I just said that the default state after PUC is MCLK, SMCLK is taken from DCODIV, and DCODIV literally means the frequency division of DCO, and the frequency division is determined by FLLD in UCSCTL2. The default state of this bit is 001, that is, 2 frequency division. So it should be MCLK=SMCLK=DCODIV=DCO/2. So the comment on TI's official website is strictly wrong. What is the default frequency of DCO? How did the above 2.097152M come from? I think the statement that the default value of DCO is 1.048576M by netizens is not accurate enough. It should be that the MCLK and SMCLK generated by using DCO are 1.048576M, not DCO itself. The default value of DCO should be doubled. Here comes something to pay attention to, FLL. The 4 and 5 series have FLL, which is not available in the 1 and 2 series. Therefore, even without an external crystal oscillator, a very stable frequency can be obtained by using the internal DCO. What is the relationship between FLL and DCO generation? I took a screenshot from the Family User's Guide of the 5/6 series (unfortunately it cannot be displayed), and saw that DCOCLK and DCOCLKDIV are output from the FLL module. From the user manual, I understand that there are two ways to generate DCO: The first is to directly configure the DCORSELx, DCOx, and MODx in the UCSCTL0 and UCSCTL1 registers to set it. Among them, DCORSELx is responsible for the selection of the DCO frequency range, DCOx is responsible for the selection of the frequency ladder, and MODx is responsible for mixing the two DCO frequencies. Since there is no FLL inside the 1 series microcontroller, the frequency of the DCO is not very accurate. From the Family User's Guide of the 5/6 series, I can see that this method of setting the DCO frequency has a large range. The second is to automatically adjust the DCO through FLL. According to the formula in the manual, fDCOCLK = D × (N + 1) × (fFLLREFCLK ÷ n) fDCOCLKDIV = (N + 1) × (fFLLREFCLK ÷ n) where D is FLLD and N is FLLN. They are both bits in UCSCTL2. n is determined by FLLREFDIV in UCSCTL3. In the default state, D is 2, N is 31, and n is 1. 7. How do we determine FLLREFCLK? This article mentioned that the FLL module is enabled, and XTI is used as the FLL reference clock FLLREFCLK. In addition, the manual also introduces REFO: the internal reference clock can be well used in situations where there is no external crystal oscillator and the cost is very sensitive. The internal reference clock can generate a very stable frequency, and its typical value is 32.768K. It can also be used as FLLREFCLK, so that the external low-frequency crystal oscillator and REFO can provide the system with flexible and changeable clocks. After PUC, XT1 cannot be used as the clock source of FLLREFCLK. I personally think that FLLREFCLK will choose REFO. Then I will verify whether I am correct. (Default D=2, N=31, n=1, FLLREFCLK=32.768K) fDCOCLK = D × (N + 1) × (fFLLREFCLK ÷ n) fDCOCLKDIV = (N + 1) × (fFLLREFCLK ÷ n) 2*(31+1)*32768=2.097152M, which is consistent with the default in the user guide.