Circuit Diagram 22-Analysis of Bistable Trigger Circuit Principle

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Circuit Diagram 22-Analysis of Bistable Trigger Circuit Principle [Copy link]

The bistable trigger is one of the basic triggers commonly used in pulse and digital circuits. The characteristics of the bistable trigger are that it has two stable states, and under the action of an external trigger signal, it can be converted from one stable state to another stable state. In the absence of an external trigger signal, the existing state will remain. The bistable trigger can be composed of a transistor, a digital circuit or a time base circuit.

1. Transistor bistable trigger

The figure below shows a transistor bistable trigger circuit

It is composed of two transistors, VT1 and VT2, which are cross-coupled. R5 and R3 are the base bias resistors of VT1, R2 and R6 are the base bias resistors of VT2, and R1 and R4 are the collector resistors of the two tubes. The output signal can be taken out from the collectors of the two transistors, and the output signals of the two tubes are opposite. The bistable trigger is essentially composed of a two-stage common emitter switch circuit and forms a positive feedback loop. The circuit is shown in the figure below. The collector output of VT2 is fed back to the base input of VT1 through R5.

1. Working process of bistable trigger

The two stable states of the bistable trigger are: either VT1 is on and VT2 is off; or VT2 is on and VT1 is off. 1) The situation when VT1 is turned on and VT2 is turned off

Because VT1 is turned on, Uc1=0V, VT2 is turned off due to no base bias current. At this time, Uc2=+VCC, and base bias current is provided to VT1 through R5 to keep VT1 turned on. As shown in the figure below, the circuit is in a stable state.

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1) The situation when VT2 is turned on and VT1 is turned off

34)]Because VT2 is turned on, Uc2=0V, VT1 is turned off due to no base bias current. At this time, Uc1=+VCC, and base bias current is provided to VT2 through R2 to keep VT2 turned on. As shown in the figure below, the circuit is in another stable state.

2. Triggering mode of bistable trigger

The triggering mode of bistable trigger is single-ended trigger and counting trigger.

1) Single-ended trigger

Single-ended trigger is to add two trigger pulses to the bases of two transistors respectively, as shown in the figure below. The single-ended trigger circuit uses the method of adding a negative pulse to the base of the conduction tube to cut it off. C1 and R7, C2 and R8 respectively form differential circuits of the two trigger pulses. Diodes VD1 and VD2 isolate the positive pulses and only allow negative pulses to be added to the base of the transistor.

The triggering process is as follows:

Assume that the circuit is in the state where VT1 is turned on and VT2 is turned off. When a pulse is added to the left trigger end, it is differentiated by C1 and R7, and its rising and falling edges generate positive and negative pulses respectively. The positive pulse is isolated by VD1, and the negative pulse is added to the base of the conduction tube VT1 through VD1 to turn it off. The cut-off of VT1 forces VT2 to turn on, and the bistable trigger is converted to another stable state. Similarly, when a pulse is added to the right trigger end, the conduction tube VT2 is turned off, VT1 is turned on, and the bistable trigger flips over again. The figure below shows the single-ended trigger working waveform. 344711 344712 b 2. Count trigger The counting trigger circuit is shown in the figure below. Unlike the single-ended trigger circuit, the counting trigger circuit has only one trigger input terminal, and the differential resistors R7 and R8 are not grounded but connected to the collector of the transistor on this side. When a trigger pulse is added to the trigger terminal, the negative pulse generated after differentiation turns off the conduction tube, but has no effect on the cut-off tube. Therefore, each trigger pulse flips the bistable trigger once. The circuit waveform is shown in the figure below. Resistors R7 and R8 play a guiding role, so that each negative pulse is only added to the base of the conduction tube to ensure reliable flipping of the circuit.

2. Bistable trigger composed of gate circuits

The gate circuit in the digital circuit can be used to easily form a bistable trigger, and no peripheral components or debugging are required. The circuit is simple and reliable.

1. RS type bistable trigger composed of NOR gates

The RS type bistable trigger can be formed by cross-coupling two NOR gate circuits. As shown in the figure below. It has two trigger input terminals: R is the reset input terminal. S is the set 1 input terminal, 1 level trigger is valid; it has two output terminals: Q is the original code output terminal.34)]When R=1, S=0, the trigger is set to 0, Q=0; when S=1, R=0, the trigger is set to 1, Q=1; when S=0, R=0, the output state of the trigger remains unchanged; when S=1, R=1, the next state is uncertain, and the trigger should be avoided from being in this state. The following figure is its truth table.

2. RS-type bistable trigger composed of NAND gates

Cross-coupling two NAND gate circuits can also form an RS-type bistable trigger, as shown in the figure below. It has two trigger input terminals: /R is the set 0 input terminal, /S is the set 1 input terminal, and 0 level trigger is valid; it has two output terminals: Q is the original code output terminal, and /Q is the inverted code output terminal.

When /R=0, /S=1, the trigger is set to 0, Q=0, /Q=1; when /R=1, /S=0, the trigger is set to 1, Q=1, /Q=0, when /R=1, /S=1, the output state of the trigger remains unchanged; when /R=0, /S=0, the next state is uncertain, and the trigger should be avoided from being in this state. The following figure is its truth table.

III. Bistable trigger composed of D trigger

Connecting the inverted output terminal /Q of the D flip-flop to its own data input terminal D constitutes a counting triggered bistable flip-flop, as shown in the figure below. The trigger pulse is input from the CP terminal and triggered by the rising edge. The output signal is usually derived from the original code output terminal Q, and can also be output from the inverted code output terminal /Q.

The figure below shows the working waveform of the bistable trigger circuit. Each rising edge of the trigger pulse causes the bistable trigger to flip once, so the number of output pulses is half of the input trigger pulse. The bistable trigger is often used as a binary counting unit circuit.

IV. Bistable trigger composed of time base circuit

The bistable trigger composed of 555 time base circuit is shown in the figure below. /S is the set 1 input terminal, 0 level trigger is valid, R is the set 0 input terminal, 1 trigger level is valid. The output signal is output from pin 3 of the 555 time base circuit. C1 and R1 constitute the /S terminal trigger signal differential circuit, and C2 and R2 constitute the R terminal trigger signal differential circuit. The working process of this circuit is: when Uo=0, when a 0-level trigger pulse is added to the /S terminal, a negative pulse is generated after differentiation by C1 and R1 to the 2nd foot of the 555 time base circuit, causing the trigger to flip, and Uo=1. After that, when a 1-level trigger pulse is added to the R terminal, a positive pulse is generated after differentiation by C2 and R2 to the 6th foot of the 555 time base circuit, causing the trigger to flip again, and Uo=0 again. The waveforms of each point of the circuit are shown in the figure below.34)]The working process of the circuit is: when Uo=0, when a 0-level trigger pulse is added to the /S terminal, a negative pulse is generated after differentiation by C1 and R1 to the 2nd foot of the 555 time base circuit, causing the trigger to flip, and Uo=1. After that, when a 1-level trigger pulse is added to the R terminal, a positive pulse is generated after differentiation by C2 and R2 to the 6th foot of the 555 time base circuit, causing the trigger to flip again, and Uo=0 again. The waveforms of each point of the circuit are shown in the figure below.

34)]The working process of the circuit is: when Uo=0, when a 0-level trigger pulse is added to the /S terminal, a negative pulse is generated after differentiation by C1 and R1 to the 2nd foot of the 555 time base circuit, causing the trigger to flip, and Uo=1. After that, when a 1-level trigger pulse is added to the R terminal, a positive pulse is generated after differentiation by C2 and R2 to the 6th foot of the 555 time base circuit, causing the trigger to flip again, and Uo=0 again. The waveforms of each point of the circuit are shown in the figure below.

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The counting triggers the RCD combination called the potential pulse gate.

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