Analysis of the Comparator Module of MSP430G2553

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Analysis of the Comparator Module of MSP430G2553 [Copy link]

MSP430G2553 has a comparator Comparator_A+ (CA+), data flow diagram DFD, state transition diagram STD[/url] 1. CA+ construction

MSP430G2553 has a comparator Comparator_A+ (CA+), and its construction block diagram is shown in the figure below.

II. Input & Output

As shown in the figure above, the comparator has a non-inverting input terminal (V+) and a reverse input terminal (V-). Through software settings, the V+ terminal can be connected to one of the three external pins CA0~CA2, or one of the three internal voltage references; the V- terminal can be connected to one of the seven external pins CA1~CA7, or one of the three internal voltage references. The internal voltage reference can be 0.5*Vcc, 0.25*Vcc, or the conduction voltage of an internal diode (about 0.55V).

The output signal can be connected to the external clock input of the Timer, or the pin corresponding to CAOUT; when the output signal changes, the CAIFG interrupt can be triggered.

The MSP430G2553 pins corresponding to CAx and CAOUT are shown in the figure below.

III. Related Setting Registers

The main registers of CA+ are CACTL1, CACTL2 and CAPD. CAPD is used to disconnect the digital circuit part connected to the GPIO pin to improve the performance of CA+; in fact, when a pin is set as CA+ input, CAPD will be automatically set, so the operation of CAPD is generally not necessary (unless the pin is also used to input a digital signal).

- P2CAx bit field of CACTL2 register: select the pin corresponding to the input signal.

- CAEx bit in CACTL1 register: switch V+, V- input signals. This function is used when the input signals are very close, and is generally not used.

- CAON bit in CACTL1 register: turn off/on CA+.

- CAREFx bit field and CARSEL bit in CACTL1 register: CAREFx bit field is used to select CA+ reference voltage, which can be 0.5*Vcc, 0.25*Vcc or ~0.55V; CARSEL bit is used to select whether the reference voltage is connected to V+ or V- terminal. Note that when V+ and V- are both connected to external pins, the internal reference voltage must be turned off.

- CAF bit in CACTL2 register: turn off/on input signal filtering. It is recommended to turn it on.

- CASHSHORT bit in CACTL2 register: short the input signal. Generally not used.

Fourth, an interesting example

Connect the potentiometer to P1.1. When the voltage of P1.1 is higher than 0.5*Vcc, the LED light flashes; otherwise, the LED light goes out. Since P1.1 corresponds to the RX of the MSP430G2553 chip, the G2 Launchpad has connected it to the USB-to-serial port chip, so when P1.1 is used as CA1, the relevant jumper on J3 should be disconnected.

[url=][/url] 1 #include "io430.h" 2 3 #define LED1 BIT0 //red 4 5 #define TRUE 1 6 #define FALSE 0 7 8 #define LOW_INPUT 0 9 #define HIGH_INPUT 110 11 //global variable12 char state = LOW_INPUT;13 char flash = FALSE; //start with low input, no flash on LED14 15 void main(void)16 {17 // Stop watchdog timer to prevent time out reset18 WDTCTL = WDTPW + WDTHOLD;19 20 // LED setup[color=rgb (0, 128, 128)]21 P1OUT = 0;22 P1DIR |= LED1;23 [color =rgb(0, 128, 128)]24 // DCO setup25 BCSCTL1 = CALBC1_1MHZ; //[color =rgb(0, 128, 0)]running at 1MHz26 DCOCTL = CALDCO_1MHZ;27 28 [color=rgb (0, 128, 0)]// ACLK setup29 BCSCTL3 |= LFXT1S_2; //ACLK source: VLO, measured as 10kHz30 BCSCTL1 |= DIVA_3; //ACLK = VLO divided by 8: 1.25kHz31 32 // Timer0_A setup33 TA0CCR0 = 250 - 1; //timer overflow freq: 1250/250 = 5Hz(0.2s)34 TA0CCTL0 = CCIE;//enable interrupt35 TA0CTL = TASSEL_1 + MC_1 + TACLR;//ACLK, no div, up mode, clear timer36 37 // Comparator_A+ setup38 CACTL1 = CAREF_2 + CARSEL + CAIE;// 0.5 Vcc ref on V-, enable interrupt on rising39 CACTL2 = P2CA4 + CAF; //[ color=rgb(0, 128, 0)]input CA1 (P1.1, remove the jumper) on V+, filter on40 CACTL1 |= CAON; //turn on comparator 41 42 __enable_interrupt();43 LPM3;44 [color =rgb(0, 128, 128)]45 }46 47 #pragma vector = TIMER0_A0_VECTOR[color=rgb (0, 128, 128)]48 __interrupt void CCR0_ISR(void)49 {[color =rgb(0, 128, 128)]50 //TA0CCR0 flag clearing is automatic51 [color= rgb(0, 0, 255)]if(flash == FALSE)52 {53 P1OUT &= ~LED1; // led off54 }55 else56 {57 P1OUT ^= LED1; //toggle LED58 }59 }60 61 #pragma vector = COMPARATORA_VECTOR62 __interrupt [color= rgb(0, 0, 255)]void COMPA_ISR(void)63 { 64 switch(state)65 {66 case LOW_INPUT:67 if((CACTL2 & CAOUT) == 0x01)68 { 69 state = HIGH_INPUT;70 CACTL1 |= CAIES; //value high, so watch for falling edge71 flash = TRUE; //let led flash 72 }[color=rgb (0, 128, 128)]73 break;74 case HIGH_INPUT:75 if((CACTL2 & CAOUT) == 0x00)76 {77 state = LOW_INPUT;[color =rgb(0, 128, 128)]78 CACTL1 &= ~CAIES; //value low, so watch for rising edge79 flash = FALSE; // turn LED off 80 }81 break; 82 }83 }[url=][/url]

This example is interesting because it demonstrates two important concepts: Data Flow Diagram (DFD) and State Transition Diagram (STD). The two interrupt programs handle interrupts from Timer0_A and CA+ respectively, forming two "processes". They have their own unique variables/parameters and also share the variable flash (whether the LED flashes). In addition, the CA+ interrupt program contains two states, HIGH_INPUT and LOW_INPUT, which is a very simple state machine.

The DFD of the program and the STD of the CA+ interrupt program are shown in the figure below.