When transistors are used as switches, capacitors are often used (bypass-input, decoupling-output, power supply, compensation capacitors in op amps)

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When transistors are used as switches, capacitors are often used (bypass-input, decoupling-output, power supply, compensation capacitors in op amps) [Copy link]

1. Basic circuit diagram of switching transistor The load resistor is directly connected between the collector of the transistor and the power supply, and is located in the loop of the main current of the transistor. The input voltage Vin controls the opening and closing of the transistor switch. When the transistor is in the open state, the load current is blocked. Conversely, when the transistor is in the closed state, the current can flow.

In detail, when Vin is a low voltage, there is no current in the base, so there is no current in the collector, resulting in no current in the load connected to the collector, which is equivalent to the opening of the switch. At this time, the transistor works in the cut-off region.

Similarly, when Vin is a high voltage, there is base current flowing, so a larger amplified current flows through the collector, so the load circuit is turned on, which is equivalent to the closing of the switch. At this time, the transistor works in the saturation region.

Regarding the switching saturation region of the crystal transistor, the saturation region of the MOS tube is the amplification region of the transistor.

The amplification of the transistor is the amplification of the current relationship, that is, Ic=B*Ib

and the amplification of the MOS tube is Ic=B*Ugs, which is related to the voltage at both ends of g and s

The amplification of the MOS tube is relatively large and stable.

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2. Selection of base resistance

（1）First determine the working state of the transistor, whether it is the amplification area (increasing driving current) or the saturation area (switching action)

（2）If it works in the amplification area, calculate the collector current according to the parameters of the collector load, then calculate the base current according to the amplification characteristics of the transistor, and then calculate the resistance according to the current value. (3) If working in the saturation region, take the NPN tube as an example to roughly calculate the selection values of a typical 3-component switch circuit: Assume that the DC gain factor of the transistor is 100, Ib = (driving voltage - 0.7Vbe junction voltage drop) / Rb, Vce = Vcc - 100Ib × Rc, let Vce = 0, from which the critical value (the critical value between the saturation region and the amplification region) can be calculated. As long as Rb is less than the critical value, but its minimum value is limited by the device Ib tolerance and must not be exceeded.

3. Compensation capacitor circuit diagram

The input parasitic capacitance Cs of a general linear amplifier (that is, an amplifier circuit that introduces negative feedback) will affect the stability of the circuit. The compensation measures are shown in the figure. The input end of the amplifier generally has a parasitic capacitance Cs of about several picofarads, and the upper frequency limit of its frequency band is approximately:

ωh=1／(2πRfCs)

In order to keep the voltage gain of the amplifier circuit high, a more common method is to connect a compensation capacitor Cf in parallel with Rf so that the RinCf network and the RfCs network form a phase compensation. RinCf will cause the output voltage phase to advance. Since the value of Cs cannot be accurately known, the phase advance and lag cannot be fully compensated. Generally, a variable capacitor Cf is used, and the additional phase shift is minimized by experiments and adjustment of Cf. If Rf=10kΩ, the typical value of Cf is 3~10pF. For voltage followers, the Cf value can be slightly larger. 3. Op amp power supply bypass capacitor

Bypass is to filter out the high-frequency clutter or signal carried by the previous stage or power supply, and decoupling is to ensure the stable output of the output end

The power lead of each integrated operational amplifier should generally adopt decoupling bypass measures, as shown in the figure. The high-frequency bypass capacitor in the figure can usually use a ceramic capacitor with excellent high-frequency performance, and its value is about 0.1μF. Or use lμF tantalum capacitors. The internal inductance of these capacitors is small. In high-speed applications of op amps, bypass capacitors C1 and C2 should be connected to the power pins of the integrated op amp, and the leads should be as short as possible to form a low inductance ground loop.

Note: When the gain bandwidth product of the amplifier used is greater than 10MHz, more stringent high-frequency bypass measures should be adopted. At this time, RF bypass capacitors should be selected. For general integrated chips, the bypass requirements are not high, but they cannot be ignored. It is usually best to add a set of bypass capacitors for every 4 to 5 devices. Regardless of the number of integrated circuit devices used, at least one set of bypass capacitors should be added to each printed board.

In the DC power supply circuit, changes in load will cause power supply noise. For example, in a digital circuit, when the circuit switches from one state to another, a large peak current will be generated on the power line, forming a transient noise voltage. Configuring decoupling capacitors can suppress the noise caused by load changes. It is a common practice for the reliability design of printed circuit boards. The configuration principles are as follows: ● A 10~100uF electrolytic capacitor is connected across the power input terminal. If the position of the printed circuit board allows, the anti-interference effect of using an electrolytic capacitor of more than 100uF will be better. ● Configure a 0.01uF ceramic capacitor for each integrated circuit chip. If the printed circuit board space is small and cannot be installed, a 1~10uF tantalum electrolytic capacitor can be configured for every 4~10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz~20MHz, and the leakage current is very small (below 0.5uA). ● For devices with weak noise capability, large current changes when turned off, and storage devices such as ROM and RAM, a decoupling capacitor should be directly connected between the power line (Vcc) and the ground line (GND) of the chip. ● The lead of the decoupling capacitor cannot be too long, especially the high-frequency bypass capacitor cannot have a lead. In the DC power supply circuit, load changes can cause power supply noise. For example, in a digital circuit, when the circuit switches from one state to another, a large peak current will be generated on the power line, forming a transient noise voltage. Configuring decoupling capacitors can suppress the noise generated by load changes, which is a common practice for the reliability design of printed circuit boards. The configuration principles are as follows: ● A 10~100uF electrolytic capacitor is connected across the power input terminal. If the position of the printed circuit board allows, the anti-interference effect of using an electrolytic capacitor of more than 100uF will be better. ● Configure a 0.01uF ceramic capacitor for each integrated circuit chip. If the printed circuit board space is small and cannot be installed, a 1~10uF tantalum electrolytic capacitor can be configured for every 4~10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz~20MHz, and the leakage current is very small (less than 0.5uA). ● For devices with weak noise resistance, large current changes when turned off, and storage devices such as ROM and RAM, a decoupling capacitor should be directly connected between the power line (Vcc) and the ground line (GND) of the chip. ●The lead of the decoupling capacitor cannot be too long, especially the high-frequency bypass capacitor cannot have a lead. In the DC power supply circuit, the change of load will cause power supply noise. For example, in a digital circuit, when the circuit switches from one state to another, a large peak current will be generated on the power line, forming a transient noise voltage. Configuring decoupling capacitors can suppress the noise caused by load changes. It is a common practice for the reliability design of printed circuit boards. The configuration principles are as follows: ●A 10~100uF electrolytic capacitor is connected across the power input end. If the position of the printed circuit board allows, the anti-interference effect of using an electrolytic capacitor of more than 100uF will be better. ●Configure a 0.01uF ceramic capacitor for each integrated circuit chip. If the printed circuit board space is small and cannot be installed, a 1~10uF tantalum electrolytic capacitor can be configured for every 4~10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz~20MHz, and the leakage current is very small (below 0.5uA). ●For devices with weak noise resistance, large current changes when turned off, and storage devices such as ROM and RAM, decoupling capacitors should be directly connected between the power line (Vcc) and the ground line (GND) of the chip. ●The leads of the decoupling capacitors should not be too long, especially high-frequency bypass capacitors should not have leads.

01uF ceramic capacitor. If the printed circuit board space is small and cannot be installed, a 1~10uF tantalum electrolytic capacitor can be configured for every 4~10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz~20MHz, and the leakage current is very small (below 0.5uA). ●For devices with weak noise capability, large current changes when turned off, and storage devices such as ROM and RAM, decoupling capacitors should be directly connected between the power line (Vcc) and the ground line (GND) of the chip. ●The leads of the decoupling capacitor cannot be too long, especially the high-frequency bypass capacitor cannot have leads. In the DC power supply loop, changes in load will cause power supply noise. For example, in a digital circuit, when the circuit switches from one state to another, a large peak current will be generated on the power line, forming a transient noise voltage. Configuring decoupling capacitors can suppress the noise caused by load changes. It is a common practice for the reliability design of printed circuit boards. The configuration principles are as follows: ● A 10~100uF electrolytic capacitor is connected across the power input terminal. If the position of the printed circuit board allows, the anti-interference effect of using an electrolytic capacitor of more than 100uF will be better. ● Configure a 0.01uF ceramic capacitor for each integrated circuit chip. If the printed circuit board space is small and cannot be installed, a 1~10uF tantalum electrolytic capacitor can be configured for every 4~10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz~20MHz, and the leakage current is very small (below 0.5uA). ● For devices with weak noise capability, large current changes when turned off, and storage devices such as ROM and RAM, a decoupling capacitor should be directly connected between the power line (Vcc) and the ground line (GND) of the chip. ● The lead of the decoupling capacitor cannot be too long, especially the high-frequency bypass capacitor cannot have a lead. In the DC power supply circuit, load changes can cause power supply noise. For example, in a digital circuit, when the circuit switches from one state to another, a large peak current will be generated on the power line, forming a transient noise voltage. Configuring decoupling capacitors can suppress the noise generated by load changes, which is a common practice for the reliability design of printed circuit boards. The configuration principles are as follows: ● A 10~100uF electrolytic capacitor is connected across the power input terminal. If the position of the printed circuit board allows, the anti-interference effect of using an electrolytic capacitor of more than 100uF will be better. ● Configure a 0.01uF ceramic capacitor for each integrated circuit chip. If the printed circuit board space is small and cannot be installed, a 1~10uF tantalum electrolytic capacitor can be configured for every 4~10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz~20MHz, and the leakage current is very small (less than 0.5uA). ● For devices with weak noise resistance, large current changes when turned off, and storage devices such as ROM and RAM, a decoupling capacitor should be directly connected between the power line (Vcc) and the ground line (GND) of the chip. ●The leads of decoupling capacitors cannot be too long, especially high-frequency bypass capacitors cannot have leads.01uF ceramic capacitor. If the printed circuit board space is small and cannot be installed, a 1~10uF tantalum electrolytic capacitor can be configured for every 4~10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz~20MHz, and the leakage current is very small (below 0.5uA). ●For devices with weak noise capability, large current changes when turned off, and storage devices such as ROM and RAM, decoupling capacitors should be directly connected between the power line (Vcc) and the ground line (GND) of the chip. ●The leads of the decoupling capacitor cannot be too long, especially the high-frequency bypass capacitor cannot have leads. In the DC power supply loop, changes in load will cause power supply noise. For example, in a digital circuit, when the circuit switches from one state to another, a large peak current will be generated on the power line, forming a transient noise voltage. Configuring decoupling capacitors can suppress the noise caused by load changes. It is a common practice for the reliability design of printed circuit boards. The configuration principles are as follows: ● A 10~100uF electrolytic capacitor is connected across the power input terminal. If the position of the printed circuit board allows, the anti-interference effect of using an electrolytic capacitor of more than 100uF will be better. ● Configure a 0.01uF ceramic capacitor for each integrated circuit chip. If the printed circuit board space is small and cannot be installed, a 1~10uF tantalum electrolytic capacitor can be configured for every 4~10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz~20MHz, and the leakage current is very small (below 0.5uA). ● For devices with weak noise capability, large current changes when turned off, and storage devices such as ROM and RAM, a decoupling capacitor should be directly connected between the power line (Vcc) and the ground line (GND) of the chip. ● The lead of the decoupling capacitor cannot be too long, especially the high-frequency bypass capacitor cannot have a lead. In the DC power supply circuit, load changes can cause power supply noise. For example, in a digital circuit, when the circuit switches from one state to another, a large peak current will be generated on the power line, forming a transient noise voltage. Configuring decoupling capacitors can suppress the noise generated by load changes, which is a common practice for the reliability design of printed circuit boards. The configuration principles are as follows: ● A 10~100uF electrolytic capacitor is connected across the power input terminal. If the position of the printed circuit board allows, the anti-interference effect of using an electrolytic capacitor of more than 100uF will be better. ● Configure a 0.01uF ceramic capacitor for each integrated circuit chip. If the printed circuit board space is small and cannot be installed, a 1~10uF tantalum electrolytic capacitor can be configured for every 4~10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz~20MHz, and the leakage current is very small (less than 0.5uA). ● For devices with weak noise resistance, large current changes when turned off, and storage devices such as ROM and RAM, a decoupling capacitor should be directly connected between the power line (Vcc) and the ground line (GND) of the chip. ●The leads of decoupling capacitors cannot be too long, especially high-frequency bypass capacitors cannot have leads.