This post was last edited by weizhongc on 2017-11-17 09:40 (The development platform hardware uses a 16M external crystal, the cpu clock is set to 48M, mcu stm32f103cbt6) In the i2c slave mode, it is found that only read operations can be performed, and it can be read all the time. If it is changed to a write operation at this time, problems will occur, and the i2c cannot be restored from the new configuration afterwards. (Host i2c read operation W_addr Reg R_addr R_data R_data) (Host i2c write operation W_addr Reg R_data R_data R_data) We thought it was a problem with the clock bus. Later we searched the clock bus and found that SYSCLK PCLK1 and the i2c clock configuration were correct. The following are the values printed out by the corresponding registers during the i2c configuration process DBG >> RCC->CFGR 53040A DBG >> I2C1->CR2 0x18 DBG >> I2C1->CR1 0x0 DBG >> I2C1->TRISE 0x8 DBG >> I2C1->CCR 0xc004 DBG >> I2C1->CR1 0x1 DBG >> I2C1->CR1 0x401 DBG >> I2C1->OAR1 0x4030 Has anyone encountered a similar problem? Please give me some advice. Thank you. I asked st's fae, and then I followed his advice and solved the problem. I just used the st cpal i2c library, and I just moved it over, and I don't need to set it up. https://my.s t.com/content/my_st_com/en/products/embedded-software/mcus-embedded-software/stm32-embedded-software/stm32-standard-peripheral-library- expansion/stsw-stm32127.license%3d1510813611433.product%3dSTSW-STM32127.html
It's done. I studied it for several days but there were always bugs. Later I asked the fae of st. They suggested using cpal library, so I used cpal library and it was done.
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