How to keep the reference voltage in the chip stable when the power supply is undervoltage

shaorc

How to keep the reference voltage in the chip stable when the power supply is undervoltage [Copy link]

As shown in the picture, as the title

Common power-off detection (BOD) or undervoltage detection (UVLO) functions inside the chip

There is a reference power supply Vref involved

However, the Vref is generated when the power is turned on normally.

So how can the Vref remain stable when the input is undervoltage or input jitter?

(I understand the principle of generating the bandgap reference voltage Vref when the power supply is normal)

maychang

Vref is generally lower than the power supply voltage, so it can be obtained from the power supply voltage through a linear regulator. Since the load current of Vref is very small, it is easy to integrate this linear regulator into the chip. With this linear regulator, Vref will not change when the power supply voltage is undervoltage, unless the power supply voltage drops below Vref.

shaorc

maychang posted on 2024-11-5 16:42 Vref is generally lower than the power supply voltage, so it can be obtained from the power supply voltage through a linear regulator. Since the load current of Vref is very small, this linear regulator...

Is the Vref mentioned here the bandgap voltage source? If so, isn't the principle of voltage regulation to generate a temperature positively correlated and a temperature negatively correlated change through a series of methods such as current mirrors to hedge and ensure voltage stability? How does that relate to the linear voltage regulation process mentioned in the second post?

maychang

shaorc posted on 2024-11-5 16:57 Is the Vref mentioned here the bandgap voltage source? If so, then the principle of voltage regulation is not to generate a temperature positive phase through a series of methods such as current mirrors...

I don't know whether the various chip models use bandgap voltage sources.

No matter which voltage source is used in the chip, it can be guaranteed that Vref remains unchanged when the chip power supply voltage changes.

zhoupxa

shaorc posted on 2024-11-5 16:57 Is the Vref mentioned here the bandgap voltage source? If so, then the principle of voltage regulation is not to generate a temperature positive phase through a series of methods such as current mirrors...

The internal reference voltage of the chip should be implemented using a bandgap voltage source, and its value is mostly around 1.2V, which is much lower than the rated power supply voltage of the chip. This part of the circuit can operate at low voltage and has a relatively high power supply rejection ratio, and can remain stable when the chip power supply voltage reaches the undervoltage value or power-off value.

shaorc

zhoupxa posted on 2024-11-5 21:10 The internal reference voltage of the chip should be realized by a bandgap voltage source, and its value is mostly around 1.2V, which is much lower than the rated power supply voltage of the chip. This part of the circuit can...

“It can remain stable when the chip power supply voltage reaches the undervoltage value or power-off value”

When the power is off, can the reference voltage value be guaranteed to be stable?

zhoupxa

shaorc posted on 2024-11-6 09:47 "When the chip power supply voltage reaches the undervoltage value or power-off value, it can remain stable" When the power is off, the reference voltage value can be guaranteed...

This power failure refers to the chip power supply Brown-Out, which can also be called undervoltage. It does not mean that the chip power supply is cut off, but the voltage is very low.