Why is there no data frame when analyzing MODBUS485 with logic analyzer?

乱世煮酒论天下

Why is there no data frame when analyzing MODBUS485 with logic analyzer? [Copy link]

I bought a logic analyzer from Zhengdian Atom, thinking of using it to analyze some communication protocols, so I tried the 485 communication on the inverter first. I first connected the computer host computer to the 485 communication port of the inverter, and the reading and writing of message frames were normal. However, when I used this computer to open the Zhengdian Atom host computer software, there was a high probability that the message frames could not be received. The logic analyzer also used two wires to directly connect to the 485 communication port of the inverter. Is it that the data acquisition input impedance of the logic analyzer affects the signal reception and transmission of the inverter?

Secondly, I set multiple thresholds for detection, including free setting thresholds, but I can't detect the ACSII binary code like a normal message frame. Do I need to share the same ground with the logic analyzer and the inverter? But the ground of the logic analyzer is connected to the negative of the 485 port. I don't know why?

lugl4313820

Do I need to share the same ground with the logic analyzer and the inverter? But the ground of the logic analyzer is connected to the negative of the 485 port. I don't know why.

The lines need to be crossed, RX and TX are crossed.

damiaa

But the ground of the logic analyzer is connected to the negative terminal of the 485 port? It should be connected to the ground of the 485 port.

乱世煮酒论天下

damiaa posted on 2024-7-24 10:28 But the ground of the logic analyzer is connected to the negative of port 485? Connect it to the ground of port 485.

Previously, it was connected to the positive and negative ends of 485. It may be that it was not connected properly, or it may be that the twisted pair cable I used was longer, about 1 meter. The host computer set the parameters, and when it was not connected to the logic analyzer computer USB port, it sent and received messages normally, but when it was connected to the logic analyzer, it only sent but did not receive.

Today I connected the logic analyzer's gnd to the gnd corresponding to the positive and negative of the main control board 485, and connected the channel to the positive end of 485, and connected the host computer software and logic analyzer at the same time. This time the transmission and reception are normal, but I want to know what the reason is? The inverter over there is not grounded, that is, gnd and the PE of the power distribution are not connected. The computer is powered by a battery, so it has nothing to do with it, and it should not be a common ground problem. The normal transmission and reception pictures are as follows:

damiaa

Luanshi Zhujiu Luntianxia published on 2024-7-24 11:42. It was connected to the positive and negative ends of 485 before. It may be that it was not connected properly, or it may be that I used a twisted pair cable that was about 1 meter long.

The logic analyzer must use the ground to judge the IO data level.

The ground of the logic analyzer cannot be connected to the AB line of RS485.

485 communication can be ungrounded. You can't connect anything else to 485 communication lines A and B. You can only connect to 485 communication A and B terminals. Terminal resistors can be connected. Of course, the input terminal of the logic analyzer has high input impedance, which doesn't matter.

乱世煮酒论天下

damiaa posted on 2024-7-24 11:46 The logic analyzer must judge the IO data level based on the ground. The ground of the logic analyzer cannot be connected to the AB line of RS485. ...

The logic analyzer received a frame of data as shown above. I sent 01 03 00 0A 00 01 A4 08 (the last four are CRC checks), 19200 baud rate, 8 data bits, even parity, 1 stop bit, but it feels that the detected bit is wrong. At a baud rate of 19200, a binary bit is about 52us, but this picture is obviously wrong. The time of each bit is too short, even only 500ns. That is, if the host computer wants to send a frame of message, should it convert this frame of message into binary in sequence, add the start bit and stop bit at the beginning and end, or load other information on the message to be sent?

乱世煮酒论天下

damiaa posted on 2024-7-24 11:46 The logic analyzer must judge the IO data level based on the ground. The ground of the logic analyzer cannot be connected to the AB line of RS485. ...

I reconnected the cables again, this time without connecting the slave device. I directly connected the USB to 485 port of the host computer to the port of the logic analyzer. The protocol analysis is as follows. This time it should be correct.

damiaa

You can use an ordinary probe to measure the uart rx tx signal end.

To measure the signal output by the RS485 chip to the 485 bus, a differential probe is probably needed (because it is a differential signal).

Generally, it is easier to measure the signal of the RS485 bus after it passes through the RS485 chip and becomes the RX, TX TTL signal, and no differential probe is required.

乱世煮酒论天下

乱世煮酒论天下published on 2024-7-24 19:48 I reconnected the line again. This time I didn't connect the slave machine. I directly connected the USB to 485 port of the host computer to the port of the logic analyzer. The protocol analysis is as follows. This...

01 03 00 0A 00 01 A4 08 converted to binary is 0000 0001 0000 0011 0000 0000 0000 1010 0000 0000 0000 0001 1010 0100 0000 0100. There are three bits in the middle of every two bytes of data information, a start bit, a check bit, and a stop bit. The start bit is always 0, the stop bit is always 1, and there is also a check bit. This is an even-parity frame structure. Look at the number of 1s in the 8-bit binary data. An odd number of 1s results in 1, and an even number of 1s results in 0. Therefore, the even-parity binary numbers of the above messages are 1 0 0 0 0 1 1 1