The chip is so small, how big can the wiring loss of the packaging substrate be?

yvonneGan

The chip is so small, how big can the wiring loss of the packaging substrate be? [Copy link]

Member of Mr. Yibo Expressway: Huang Gang

Compared to a PCB carrier, the size of the chip package substrate inside the PCB may only occupy a small part of it. Then, comparing the traces on the package substrate and the traces on the PCB, the length may be at least several times longer. So do you think that the traces on the package substrate are so short that the loss can be almost ignored? Especially when asking engineers who have only been exposed to PCB board design, most people answer that the loss of the package should be very small.

This article will answer this question through a specific simulation case. Mr. Gaosuo's team is currently simulating a PCIE4.0 board project, including the co-simulation of the package substrate of the main control chip and the PCB carrier. The PCIE trace on the PCB carrier is from the main control chip to the gold finger position, and the length ranges from 2-3 inches.

As an object to be simulated, we definitely need to know the loss standard of the PCIE4.0 link. So Mr. Gaosuo immediately looked up the relevant PCIE protocol standard and found that it defines the loss of the gold finger link as follows. The protocol clearly states that the loss from the die of the main control chip to the PCIE gold finger position on the carrier board does not exceed 8db@8GHz, which means that this 8db includes the sum of the routing link on the package substrate and the routing link from the carrier board to the gold finger end.

This protocol seems to be very clear, but it is actually not that clear, because it does not clearly distinguish between the loss distribution of the routing on the package substrate and the routing on the carrier board. Fortunately, in our project, we can get both the package substrate and carrier board files, so we can do a joint simulation.

So we first looked at the routing of the package substrate and the length of the carrier board. After opening the package substrate, we selected the longest lane and measured its routing length. We were shocked to find it was so short, just over 600mil. Yes, this length is indeed very short for engineers who are used to making board-level PCBs.

Therefore, compared with the length on the package substrate, the trace length on the carrier board is almost 5 times the length of the substrate, close to 3000 mil.

By comparing the length of the substrate and board-level traces, does it mean that the substrate trace loss is only one-fifth of the board-level trace loss?

Of course, if all other conditions are the same, then it is definitely the case. So the question is, even if the substrate and carrier are made of the same material, will their losses be in this proportional relationship? Of course not, because in addition to the same material, the line width and copper thickness must also be the same. However, those who have worked on packaging substrates know that how can the line width be the same? If they are the same, then the packaging substrate may be smaller and thinner than the carrier?

So how thin can the traces on the package substrate be? I think those who have only worked as PCB engineers probably can’t imagine that it is only... 20um!!! That is less than 0.8mil!

What is the width of the trace that connects to the carrier through the substrate? That is the line width we are familiar with, which is more than 4mil.

Then the question is, how big a loss difference can the difference in line width bring? We set the stacking and line width, copper thickness, and roughness parameters of the package substrate and board level in the sigrity software. In order to compare the impact of line width, we unify the roughness, copper thickness, and board material. We uniformly choose ordinary FR4 material for the board. The stacking on the substrate is shown below:

Then, the loss is calculated based on the package substrate length of 624 mil and the carrier length of 2774 mil. The result will shock you! The substrate routing loss of more than 600 mils is more than half of the carrier routing loss of nearly 3000 mils.

From this point of view, you may think that the carrier board is still larger, which is not very intuitive. Then I will make the carrier board have the same length of more than 600 mil as the package substrate, and then compare the loss of the two, you will know the difference! Under the same length, the wiring loss of the substrate is 2.4 times that of the carrier board!

Moreover, the simulation comparison verification above is based on the case where the copper thickness is set to the same. Generally speaking, the copper thickness of the substrate will be smaller than the 0.5Oz of the carrier board. In this case, the gap will be further widened!

Through the above simple simulation, I believe everyone will probably know the difference in loss between the package substrate and the carrier. When you encounter the protocol loss distribution of the package and the carrier in the future, don't think that it is only determined by the chip size or the package trace length. The loss of the package substrate is limited by the area and thickness, and the line width must be very small. The difference in line width alone may reach 2 to 3 times the loss difference! So friends, if you still think that the loss of the package substrate accounts for a small proportion, this concept must be changed!

led2015

Indeed, the losses of many boards are not what you think. Small size does not necessarily mean poor heat dissipation.

wsmysyn

A few days ago, I had a meeting with my colleagues who were working on the system. I listened to the various professional questions raised by the big guys and gained a deeper understanding of various aspects such as chip packaging and board-level design.

When the power consumption of the chip reaches hundreds of watts and the data rate exceeds tens of Gbps, every link is very important and cannot be taken for granted.