rk3568 Hardware Development Notes (Part 4) SSD Circuit Design

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rk3568 Hardware Development Notes (Part 4) SSD Circuit Design [Copy link]

rk3568 Hardware Development Notes (Part 4) SSD Circuit Design

The development board uses a standard PCIe3.0 connector, which can be used to install external PCIe boards for communication.

Working mode: Root Complex (RC).

The link supports 4 lane data interface.

The 100MHz clock is provided by an external clock chip.

Section 1: PCIe3.0 interface CPU side

The main networks include 2 groups of TX, 2 groups of RX, 1 group of clk, and 1 group of power supply, which are 0.9V and 1.8V respectively;

The differential line needs to be 100 Ohm impedance controlled, where R500 is the reference resistor to adjust the driving capability;

Section 2: PCIE 3.0 interface circuit

illustrate:

1. The interface adopts M.2 connector, interface type M-KEY, 75PIN;

2. 2 groups of TX signals plus coupling capacitors, generally 100pf;

3. Other signals include reset, wake-up, and reference clock;

4. PCIE3.0 is connected to SSD by default, the current is generally within 3A and the voltage is 3.3V;

Section 3: RK3568 PCIE3.0 Processing of CLK

The RK development document clearly states that when PCIE30 is connected to the EP device, the CLK signal needs to be connected externally.

Therefore, the PI6C557-03BLE clock generator is added.

Clock generator peripheral circuit description:

1. The clock generator pins 1 2 3 8 are configured through pull-up/pull-down resistors.

2. An external 25MHZ crystal oscillator is required, and the matching capacitor is 8.2pf;

3. If the motherboard adopts 50ohm impedance

Then R2016 = 475ohm provides IREF = f 2.32 mA. Output current ( IOH ) i = 6 * IREF .6x2.32X50=696mV

4. Add 33R matching resistors to the clock signal input and output, and 49.9R to the docking;

Attached photos

The above circuit design is based on the Xinchuangyun R680A-Q2 development board shown below

lugl4313820

The above circuit design is based on the Xinchuangyun R680A-Q2 development board shown in the figure below. This is the first time I have heard of this.