I need help from seniors on the number of Verilog LUTs

zzw_rst

I need help from seniors on the number of Verilog LUTs [Copy link]

I would like to ask how many LUTs these modules have. Since I am a novice, I don’t know which functions are integrated. I need to explain the source of the functions in more detail.

Then what is the delay and how many levels of LUT.

Note: The last two pictures have example calls.

卿小小

//------illustrate

If it is not a tutor's homework, the value of this code is not very high. If you want to learn Verilog or FPGA, it is recommended to start with the tutorial of the development board.

In order to improve communication efficiency, it is recommended to use source files or insert text to process content such as code, and try not to post code pictures.

//------process

Here we only use the first picture "Vr1to8check" to explain the process and function. The processing of the other files is similar.

//---Basic steps:

1.创建工程，器件型号任意选择（此处我选择的xc7k325tffg900-2）。
2.新建源文件或者导入源文件，源文件内是需要测试验证的代码。
3.运行综合Synthesis，等待运行结束查看综合后资源占用结果。
4.同时，在RTL_ANALYSIS/Open_Elaborated_Design中可以对RTL进行更加详细的网表分析。

//---Steps example:

//---Source file

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/12/14 17:00:57
// Design Name: 
// Module Name: Vr1to8check
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module Vr1to8check(
    input       [0:7]       I       ,//input
    output reg              VALID    //output
    );
    //------internal_signals: reg, wire, integer.
    integer                 N1s     ;
    integer                 j       ;
    
    //------always
    always@(I) begin
        N1s = 0 ;
        for(j = 0 ; j <= 7 ; j = j + 1) N1s = N1s + I[j] ;//for()
        VALID = (N1s == 1);
    end
    //a. when "I" is changed, first N1s is changed to "0";
    //b. then N1s will execute “for”，which means: N1s+I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6]+I[7];
    //c. at the end, VALID=1 @N1s=1, VALID=0 @N1s=0.
    
    //------
    
endmodule

zzw_rst

Qing Xiaoxiao published on 2022-12-14 17:53 //------If it is not a tutor's homework, the value of this code is not very high. If you want to learn Verilog or FPGA, it is recommended to start from the tutorial of the development board...

Thanks for the reply.

The first and second pictures have the same function, the LUT number is 3vs4, did I get it wrong or is it a version problem?

I think it's better if I can calculate the LUT number myself, and I also need to compare it with the machine. If there are many codes to be integrated and need to be selected, it may take more time to type them in. I don't know if I am right.

becauseeveninthissimpleexample(justan8-inputfunction)Vivadodoesnotsearchtheentire"solutionspace"forthebestimplementation,andtheresultsdependverymuchonthestartingpoint.“startingpoint”是什么。

The fastest implementation method should not depend entirely on the number of LUTs, but on what factors may influence it.

卿小小

zzw_rst published on 2022-12-15 14:41

The result of synthesis is not very meaningful, and the final result should be based on the Implementation layout and routing.

At the same time, in order to prevent Implementation from automatically optimizing resources, many internal variables in the code may need to be simply processed, mainly by adding statements such as (*keep="true"*) at the front end of the corresponding internal variable definition to prevent them from being optimized away.

I don't quite understand what "starting-point" means.

I arbitrarily speculate that the "starting-point" is the initial entry point for physical layout and routing. Simple layout and routing is not difficult, and there is no need to consider the entry point. The final routing and resource results are basically similar. When encountering complex parts (such as using a large number of generate or for loops), the timing of the part that is initially optimized will be better; the subsequent optimized part may deteriorate the corresponding logic timing.