Xianji official engineer dry goods: HPM6700/6400 series network-based IEE1588 function examples and usage guide

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Xianji official engineer dry goods: HPM6700/6400 series network-based IEE1588 function examples and usage guide [Copy link]

 

The HPM6700/6400 series microcontrollers provide two Ethernet controllers, both of which support IEEE1588-2002 and IEEE1588-2008 standards, making it easy for users to achieve precise time synchronization based on the network.

This article provides functional examples and usage guidelines for the network-based IEE1588 with the HPM6700/6400 series microcontrollers.

Introduction to IEEE1588

The full name of IEEE1588 is the precision time synchronization protocol standard (PTP – Precision Time Protocol) for network measurement and control systems. There are currently two versions, IEEE1588 (v1) and IEEE1588 (v2) . The purpose of IEEE1588 is to synchronize the clocks of all devices in the network, which is particularly important for the control and acquisition synchronization of network devices. This section briefly introduces the basic knowledge of IEEE1588. For detailed protocol descriptions, please refer to the relevant website.

1. 1588 Synchronization Principle

The principle of 1588 is that the master device in the network sends a special message to the slave device and interacts with the slave device to obtain the time deviation to further synchronize the device clock. As shown in the following figure:

The master port sends a synchronization message at time t1, and sends the time of point t1 in the next message. The slave port receives the synchronization message at time t2 and sends a response to the master port at time t3. After receiving the response from the slave port, the master port sends time t4 to the slave port.

In this process, network delay and clock skew are obtained.

Toffset = ((t2 - t1) + (t4 - t3)) / 2

Tdelay = ((t4 - t1) - (t3 - t2)) / 2

In the entire network topology, all nodes perform clock synchronization regularly, ultimately achieving nanosecond (IEEE1588-2008) or microsecond (IEEE1588-2002) accuracy.

HPM67/64 Series 1588 Function Introduction

IEEE1588 itself is proposed based on Ethernet, so its detailed usage and register description can be found in Chapter 60 of the HPM6700/6400 User Manual .

To use the 1588 function, you must first assign a clock source to the function. Because the HPM6700/6400 has two Ethernet controllers, ENET0 and ENET1. Therefore, the controller sets up two clock sources for 1588 , which are:

CLOCK_TOP_PTP0;

CLOCK_TOP_PTP1.

On the HPM6700/6400 microcontroller, CLOCK_TOP_PTP0/1 is used as the operating clock of the 1588 time stamp counter of ENET0/1 respectively . The default frequency selection is to use the output of PLL1CLK1 . The default output of PLL1CLK1 is 400MHz , and the default clock division factor is 4. Therefore, the default frequency of CLOCK_TOP_PTP0/1 is 100MHz . Users can set different frequencies as input according to their needs.

clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4);
clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4);

The user needs to set the following registers to implement the corresponding 1588 functions

• TS_CTRL Timestamp Control Register

• SUB_SEC_INCR Sub-second increment register

• SYST_SEC System time – seconds register

• SYST_NSEC System time – nanosecond register

• SYST_SEC_UPD System Time – Seconds Update Register

• SYST_NSEC_UPD System Time – Nanosecond Update Register

• TS_ADDEND Timestamp addition register

After determining the input frequency, the user needs to fill in the increment value in SUB_SEC_INCR. Its filling mainly depends on two factors, one is the 9th bit TSCTRLSSR in TS_CTRL, and the other factor is the input frequency mentioned above.

TSCTRLSSR is the counting mode selection. When it is set to 1, the SYS_NSEC nanosecond register flips when it reaches 0x3B9AC9FF; when it is set to 0, the SYS_NSEC nanosecond register flips when it reaches 0x7FFFFFFF. Each flip of SYS_NSEC represents 1 second in time. Therefore, when TSCTRLSSR is set to 1, 1 in SYS_NSEC represents 1ns; when TSCTRLSSR is set to 0, 1 in SYS_NSEC represents 0.465ns. The number in SUB_SEC_INCR.SSINC represents the time corresponding to the input frequency, which will be converted accordingly according to the time represented by 1 count in SYS_NSEC.

For example, when the input frequency is 100MHz , one clock is 10ns . When TSCTRLSSR is set to 1 , SUB_SEC_INCR.SSINC is set to 10 (10/1) ; when TSCTRLSSR is set to 0 , SUB_SEC_INCR.SSINC is set to 21 (10/0.465) .

It is recommended that users set TSCTRLSSR to 1, which is easier to understand and calculate.

SYST_SEC and SYST_NSEC are timestamps maintained by MAC. SYST_SEC is a timestamp in seconds, and SYST_NSEC is a timestamp in nanoseconds. SYS_NSEC will flip under different data according to the setting of TSCTRLSSR. When TSCTRLSSR is set to 1 , it will flip at 0x3B9AC9FF , and when TSCTRLSSR is set to 0 , it will flip at 0x7FFFFFFF .

SYST_SEC_UPD and SYST_NSEC_UPD are registers for updating the timestamp. If you need to reduce the nanosecond time, you need to set the highest bit in SYST_NSEC_UPD to 1. If you need to increase the nanosecond time, you need to set the highest bit in SYST_NSEC_UPD to 0.

Assume that the clock synchronization algorithm finds that the clock is too slow and wants to adjust the accumulated step size to 10.1 ns. In this case, you can keep SUB_SEC_INCR.SSINC to 10 and set ADDEND = 0xFFFFFFFF * (0.1) = 0x19999999 . At this point, the equivalent accumulated step size can be considered to be 10.1 ns.

Assume that the clock synchronization algorithm finds that the clock is too fast and wants to adjust the accumulated step size to 9.9 ns. In this case, you need to set SUB_SEC_INCR.SSINC to 9 and set ADDEND = 0xFFFFFFFF * (0.9) = 0xE6666666 . At this point, the equivalent accumulated step size can be considered to be 9.9 ns.

Note that all the above registers need to be written by setting the corresponding status bit in TS_CTRL to 1, and when this bit is 0, it is considered that the setting is successful.

In the SDK provided by Xianji, you can directly call

../../hpm_sdk/drivers/src/hpm_enet_drv.c for settings

void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config)
void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp)

1588 Routine Analysis

In the SDK released by Xianji, you can find the implementation routine v1 of 1588 (ie IEEE1588-2002)

..\..\hpm_sdk\samples\lwip\lwip_ptp\v1

It includes master and slave, corresponding to the master port and slave port respectively. Without changing any settings, the user needs 2 pieces for testing, one as the master port and the other as the slave port. In order to test the clock synchronization performance of IEEE1588, we used 2 HPM6750EVKs and burned the master and slave programs respectively.

It should be noted that the IP addresses of the two boards should be different. The default routine uses the RMII PHY on the board, and users can replace it with RGMII PHY for testing according to their own needs .

1. Code Analysis

Initialize the system, first initialize the IO, Ethernet chip and set the 1588 clock.

board_init();
board_init_enet_ptp_clock(ENET);
board_init_enet_pins(ENET);
enet_init(ENET);

After successfully initializing the Ethernet chip, initialize lwip, set network parameters, ptp clock

enet_ptp_init();
lwip_init();
netif_config();
user_notification(&gnetif);
ptpd_Init();

Receive network clock synchronization data packets and use them to correct the clock.

while (1) {
ethernetif_input(&gnetif);
         ptpd_periodic_handle(localtime);
｝

2. Test Methods

Because the precise clock synchronization function of 1588 needs to be implemented in the network, two HPM6750EVKs were used for testing by docking. After the master and slave programs were burned in respectively, the RJ45 (J10) port on the board was directly connected via a network cable. As shown in the figure:

After the system is powered on, the serial port of the slave port displays

(D 1651074120.060559130) state PTP_SLAVE
(D 1651074121.919880830) addForeign: new record (0,1) 1 1 98:2c:bc:b1:9f:18
(D 1651074121.923243890) event MASTER_CLOCK_CHANGED
(D 1651074121.925549510) state PTP_UNCALIBRATED
(D 1651074121.927681110) toState: Q = 0, R = 5
(D 1651074123.919898550) updateOffset
(D 1651074123.921597570) updateClock seconds
(D 1651074134.003162180) setTime: resetting system clock to 1651074134s 3162050ns
(D 1651074134.006781080) initClock
(D 1651074134.008349500) one-way delay:           0s          0ns
(D 1651074134.011270660) offset from master:      -10s  -79562820ns
(D 1651074134.014279260) observed drift:          0
(D 1651074135.999474620) updateOffset
(D 1651074136.001174640) one-way delay:           0s          0ns
(D 1651074136.004096190) offset from master:      0s      10170ns
(D 1651074136.007017370) observed drift:          169
(D 1651074137.999480800) updateOffset
(D 1651074138.001180620) one-way delay:           0s          0ns
(D 1651074138.004101330) offset from master:      0s      14370ns
(D 1651074138.007022680) observed drift:          408

3. Test results

By comparing the results, we compare the offset values of the timestamps and get the following figure:

As can be seen from the figure, at the beginning of synchronization, the time deviation is large, but after the initial rapid adjustment, the clock accuracy is within ±10us. This is already a very good effect for IEEE1588-2002.

Summarize

This article introduces the use of Ethernet 1588 functions of HPM6700/6400 series microcontrollers and demonstrates examples. Good results were obtained in the 100MHz network test under IEEE1588-2002. The test of 1588-2008 version will be introduced in subsequent documents.

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Jacktang

Synchronous start, the time deviation is large, the clock accuracy is large and the effect may be poor