Allwinner V853 development board Tina SDK LCD small resolution DCLK setting problem

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Allwinner V853 development board Tina SDK LCD small resolution DCLK setting problem [Copy link]

 

**1. Topic** Tina SDK LCD small resolution DCLK setting**2. Problem background** Product: Product with display Hardware: V series + DE Software: Tina SDK Others: Using a small-resolution LCD display frequency, the DLCK calculated according to the LCD timing is less than 48MHz **3. Specific performance** It can be seen that the desired dlck is 10MHz, but the lck real dclk is 18MHz, resulting in abnormal subsequent frame rate display``` [ 0.186329] disp 0, clk: pll(40000000),clk(40000000),dclk(10000000) dsi_rate(10000000) [ 0.186329] clk real:pll(72000000),clk(72000000),dclk(18000000) dsi_rate(18000000) ``` View information: ``` root@(none):/sys/devices/virtual/disp/disp/attr# cat sys screen 0: de_rate 300000000 hz, ref_fps:50 mgr0: 272x480 fmt[rgb] cs[0x204] range[full] eotf[0x4] bits[8bits] err[0] force_sync[0 ] unblank direct_show[false] dmabuf: cache[0] cache max[0] umap skip[0] overflow[0] lcd output backlight(255) fps:90.9 272x 480 err:0 skip:170 irq:22509 vsync:0 vsync_skip:0 BUF enable ch[0] lyr[0] z[2] prem[N] 128] fmt[ 77] fb[ 272, 480; 136, 240; 0, 0] crop[ 0, 0, 272, 480] frame[ 0, 0, 272, 480] addr[ 2e0000, 2d0000, 0] flags[0x 0] trd[0,0] BUF enable ch[2] lyr[ 0] z[16] prem[N] a[pixel 150] fmt[ 0] fb[ 272, 480; 272, 480; 272, 480] crop[ 0, 0, 272, 480] frame[ 0, 0, 272, 480] addr[ 17f800, 0, 0] flags[0x ``` **4. Problem Analysis** When the LCD uses a small resolution, according to the timing parameters required by the LCD, the calculated dlck will generally be less than 48MHz, or even smaller. At this time, the dclk calculated by the customer will be very small, and may not be divisible by 24. Then the dclk is directly set, such as setting lcd_dclk_freq = <10>; the default frequency division coefficient of the driver bottom layer is 4, so the theoretical calculated value of the pll value is 40MHz, and the actual LCD PLL is obtained by multiplying 24MHz, and 40MHz is not a multiple of 24, so the frequency of the PLL will be taken upwards, and the calculated value here is 72MHz, and then the actual dlck obtained by 4 division is 18MHz, which causes the LCD to be abnormal. **5. Root Cause** A frequency that cannot divide 24MHz is set in the small resolution dts. **6.Solution** When setting DCLK for a small-resolution LCD, try to set the calculated theoretical value of dclk to the following frequency values: 48MHz 24MHz 12MHz 8MHz 6MHz 4MHz When setting the dclk of condition 1, if the displayed frame rate or display is still abnormal, just set it according to the calculated theoretical value. For example, if the calculated dclk value is 10MHz, then set lcd_dclk_freq = <10> in dts; and then adjust the division factor according to the startup log, as follows: ``` [ 0.186329] disp 0, clk: pll(40000000),clk(40000000),dclk(10000000) dsi_rate(10000000) [ 0.186329] clk real:pll(72000000),clk(72000000),dclk(18000000) dsi_rate(18000000) ``` From the printout, we can see that the frequency division system is now 4-division: pll/dclk=4, so if we want to get a frequency close to 10MHz, we can change the frequency division factor to 6 or 8, 72/6=12, 72/8=9. Modify the frequency division coefficient``` 3.1 kernel(drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v2x/disp_al.c) static struct lcd_clk_info clk_tbl[] = { {LCD_IF_HV, 6, 1, 1, 0}, /* CPU interface/ {LCD_IF_CPU, 12, 1, 1, 0}, / LVDS interface/ {LCD_IF_LVDS, 7, 1, 1, 0}, #if defined(DSI_VERSION_40) {LCD_IF_DSI, 4, 1, 4, 148500000}, #else / mipi interface/ {LCD_IF_DSI, 4, 1, 4, 0}, / Change to 8 division {LCD_IF_DSI, 8, 1, 8, 0}*/ #endif /endif DSI_VERSION_40/ {LCD_IF_VDPO, 4, 1, 1, 0}, }; 3.2 uboot (drivers/video/sunxi/disp2/disp/de/lowlevel_v2x/disp_al.c) static struct lcd_clk_info clk_tbl[] = { {LCD_IF_HV, 6, 1, 1, 0}, { LCD_IF_CPU, 12, 1, 1, 0}, {LCD_IF_LVDS, 7, 1, 1, 0}, #if defined(DSI_VERSION_40) {LCD_IF_DSI, 4, 1, 4, 150000000}, #else {LCD_IF_DSI, 8, 1, 8, 0}, #endif /*endif DSI_VERSION _40 */ }; ```

Jacktang

It turns out that the problem is that the frequency set in this small resolution DTS cannot be divided into 24MHz.

freebsder

It’s so hard to adjust the LCD, thank you for sharing!