Release time
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2016
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2020
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2020
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2020
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Product Model
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Please refer to the ESP32 Technical Specification (PDF)
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Please refer to the ESP32-S2 Technical Specification (PDF)
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Please refer to the ESP32-C3 Technical Specification (PDF)
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Please refer to the ESP32-S3 Technical Specification (PDF)
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Kernel
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Equipped with low-power Xtensa LX6 32-bit dual-core/single-core processor
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Equipped with low-power Xtensa LX7 32-bit single-core processor
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Equipped with RISC-V 32-bit single-core processor
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Equipped with low-power Xtensa LX7 32-bit dual-core processor
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Wi-Fi Protocols
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802.11 b/g/n, 2.4 GHz
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802.11 b/g/n, 2.4 GHz
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802.11 b/g/n, 2.4 GHz
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802.11 b/g/n, 2.4 GHz
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Bluetooth
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Bluetooth v4.2 BR/EDR and Bluetooth Low Energy
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Bluetooth 5.0
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Bluetooth 5.0
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Frequency
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240 MHz (160 MHz for ESP32-S0WD)
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240 MHz
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160 MHz
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240 MHz
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SRAM
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520 KB
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320 KB
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400 KB
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512 KB
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ROM
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448 KB for program startup and kernel function calls
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128 KB for program startup and kernel function calls
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384 KB for program startup and kernel function calls
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384 KB for program startup and kernel function calls
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Embedded flash
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2 MB, 4 MB or no embedded flash, varies by model
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2 MB, 4 MB or no embedded flash, varies by model
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4 MB or no embedded flash, varies by model
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8 MB or no embedded flash, varies by model
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External flash
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Supports up to 16 MB, and can map up to 11 MB + 248 KB at a time
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Supports up to 1 GB, and can map up to 11.5 MB at a time
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The maximum supported size is 16 MB, and a maximum of 8 MB can be mapped at a time
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Supports up to 1 GB, and can map up to 32 MB at a time
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Off-chip RAM
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Supports up to 8 MB, and can map up to 4 MB at a time
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Supports up to 1 GB, and can map up to 11.5 MB at a time
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Supports up to 1 GB, and can map up to 32 MB at a time
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Cache
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2-way group associative
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4-way set associative, independent instruction and data caches
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8-way group-connected, 32-bit data/instruction bus width
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Instruction cache can be configured as 4-way set associative or 8-way set associative, data cache is fixed as 4-way set associative, 32-bit data/instruction bus width
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Peripherals
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|
|
|
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Analog-to-digital converter (ADC)
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Two 12-bit SAR ADCs, up to 18 channels
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Two 12-bit SAR ADCs, up to 20 channels
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Two 12-bit SAR ADCs, supporting up to 6 channels
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Two 12-bit SAR ADCs, up to 20 channels
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Digital-to-Analog Converter (DAC)
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Two 8-bit channels
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Two 8-bit channels
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|
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Timer
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Four 64-bit general-purpose timers, three watchdog timers
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Four 64-bit general-purpose timers, three watchdog timers
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2 54-bit general-purpose timers, 3 watchdog timers
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4 54-bit general-purpose timers, 3 watchdog timers
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Temperature Sensor
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1
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1
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1
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Touch Sensor
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10
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14
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14
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Hall sensor
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1
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|
|
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General Purpose Input/Output (GPIO)
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34
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43
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twenty two
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45
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Serial Peripheral Interface (SPI)
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4
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4
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3
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4
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LCD Interface
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1
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1
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1
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Universal Asynchronous Receiver/Transmitter (UART)
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3
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twenty one
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twenty one
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3
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I2C Interface
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2
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2
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1
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2
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I2S Interface
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2, configurable as 8/16/32/40/48-bit input and output channels
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1, configurable as 8/16/24/32/48/64-bit input and output channels
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1, configurable as 8/16/24/32-bit input and output channels
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2, configurable as 8/16/24/32-bit input and output channels
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Camera Interface
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1
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1
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1
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DMA
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UART, SPI, I2S, SDIO slave, SD/MMC host, EMAC, BT and Wi-Fi all have dedicated DMA controllers
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UART, SPI, AES, SHA, I2S and ADC controllers all have dedicated DMA controllers
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General purpose DMA controller, 3 receive channels and 3 transmit channels
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General purpose DMA controller, 5 receive channels and 5 transmit channels
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Infrared Remote Control (RMT)
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Support 8 channels
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Supports 4 channels 1 , configurable as infrared transmitter and receiver
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Support 4 channels 2 , dual channel infrared transmission and dual channel infrared reception
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Supports 8 channels 1 , configurable as infrared transmitter and receiver
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Pulse counter
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8 channels
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4 Channel 1
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4 Channel 1
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LED PWM
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16 channels
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8 Channel 1
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6 Channel 2
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8 Channel 1
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MCPWM
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2. Provide six PWM outputs
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|
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2. Provide six PWM outputs
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USB OTG
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1
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1
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TWAI controller (compatible with ISO 11898-1 protocol)
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1
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1
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1
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1
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SD/SDIO/MMC Host Controllers
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1
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|
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1
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SDIO Slave Controller
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1
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|
|
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Ethernet MAC interface
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1
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|
|
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Ultra-low-power coprocessor (ULP)
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ULP FSM
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PicoRV32 core, 8 KB SRAM, ULP FSM
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PicoRV32 core, 8 KB SRAM, ULP FSM
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Assisted debugging
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|
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1
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Safety Mechanism
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|
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Secure Boot
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Faster and safer than ESP32
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Faster and safer than ESP32
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Faster and safer than ESP32
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Flash Encryption
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Supports PSRAM encryption, more secure than ESP32
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More secure than ESP32
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Supports PSRAM encryption, more secure than ESP32
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OTP
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1024 bits
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4096 bits
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4096 bits
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4096 bits
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AES
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AES-128, AES-192, AES-256 (FIPS PUB 197)
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AES-128, AES-192, AES-256 (FIPS PUB 197); supports DMA
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AES-128, AES-256 (FIPS PUB 197); DMA support
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AES-128, AES-256 (FIPS PUB 197); DMA support
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HASH
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SHA-1, SHA-256, SHA-384, SHA-512 (FIPS PUB 180-4)
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SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); supports DMA
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SHA-1, SHA-224, SHA-256 (FIPS PUB 180-4); supports DMA
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SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); supports DMA
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RSA
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Up to 4096 bits
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Up to 4096 bits
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Up to 3072 bits
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Up to 4096 bits
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Random Number Generator (RNG)
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|
|
|
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HMAC
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|
|
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Digital Signature
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|
|
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XTS
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XTS-AES-128, XTS-AES-256
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XTS-AES-128
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XTS-AES-128, XTS-AES-256
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other
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|
|
|
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Deep-sleep power consumption (ultra-low power consumption sensor monitoring method)
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100 μA (ADC operating at 1% duty cycle)
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22 μA (when touch sensor operates at 1% duty cycle)
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No such mode
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TBD
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Package size
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QFN48 5*5, 6*6, different models have different
|
QFN56 7*7
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QFN32 5*5
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QFN56 7*7
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