How to design multi-rail power supply for application circuit boards

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How to design multi-rail power supply for application circuit boards [Copy link]

By: Analog Devices | Ching Man, Applications Engineer

Introduction: Challenges facing engineers in an era of continuous development

Tight schedules sometimes cause engineers to ignore other key details besides VIN, VOUT, and load requirements, leaving the power design for PCB applications as an afterthought. Unfortunately, these previously overlooked details can become difficult to diagnose problems when the PCB is subsequently produced. For example, after a long debugging process, designers discover that the circuit will randomly fail, for example, because of switching noise, and the source of the random failure is difficult to track down.

This article is the first in a two-part series that looks at some of the issues that can be overlooked when designing a multi-rail power supply. While the first part focused on strategies and topologies, the second part will focus on the details of power budgeting and board layout, as well as some design tips. Many application boards use power supplies to bias multiple logic levels, and this series will explore multi-supply board solutions. Design topologies or strategies that aim to get it right the first time.

Wide selection

For a particular power supply design, there may be multiple viable solutions. In the following examples, we will look at multiple options, such as single-chip power supplies versus multi-rail integrated circuits (ICs). We will evaluate cost and performance trade-offs. We will explore the trade-offs between low dropout (LDO) regulators and switching regulators (generally referred to as buck or boost regulators). We will also look at hybrid approaches (i.e., mixing and matching LDO and buck regulators), including voltage input to output control (VIOC) regulator solutions.

In this article, we will analyze switching noise and how the PCB circuit will be affected when the switching power supply design cannot be adequately filtered. From an overall design perspective, factors such as cost, performance, implementation, and efficiency also need to be considered.

For example, how do you optimize your design for a multi-supply topology given one or more supplies? We will take a deep dive into design, IC interface techniques, voltage threshold levels, and what types of regulator noise can affect your circuit. We will analyze some basic logic levels, such as 5 V, 3.3 V, 2.5 V, and 1.8 V transistor-transistor logic (TTL), complementary metal oxide semiconductor (CMOS), and their respective threshold requirements.

Advanced logic such as positive emitter coupled logic (PECL), low voltage PECL (LVPECL), and current mode logic (CML) are mentioned but not covered in detail. These are very high-speed interfaces for which low noise levels are very important. Designers need to know how to avoid these problems caused by signal swings.

In power supply design, cost and performance requirements coexist, so designers must carefully consider logic levels and requirements for clean power. Production problems can also be avoided by designing for reliability and providing appropriate margins in terms of tolerance and noise.

Designers need to understand the trade-offs associated with power supply design: What is achievable? What is acceptable? If the design does not achieve the required performance, then the designer must re-examine the options and costs to meet the specifications. For example, multi-rail devices such as the ADP5054 from Analog Devices can provide the required performance benefits while remaining cost-effective.

Typical design examples

Let’s start with a design example. Figure 1 shows a board block diagram with 12 V and 3.3 V input supplies as the main power supplies. The main power supply must be stepped down to generate 5 V, 2.5 V, 1.8 V, or even 3.3 V for PCB applications. If the external 3.3 V supply can provide sufficient power and low noise, then the 3.3 V input rail can be used directly without additional regulation and incurring additional cost. If not, then the 12 V input rail can be used and the power supply requirements can be met by stepping down to the 3.3 V required for the PCB application.

Figure 1. Overview of an application board requiring a multi-rail power solution

Logical Interface Overview

PCBs typically use multiple power supplies. The IC may use only 5 V; or it may require multiple supplies, 5 V and 3.3 V for the input/output interface, 2.5 V for the internal logic, and 1.8 V for low-power sleep mode. The low-power mode may be always on for timer functions, housekeeping logic, etc., or for wake-up mode on interrupts, or for IRQ pins to enable and power IC functions, that is, 5 V, 3.3 V, and 2.5 V supplies. All or some of these logic interfaces are usually internal to the IC.

Figure 2 shows the standard logic interface levels, including various TTL and CMOS threshold logic levels, and their acceptable input and output voltage logic definitions. In this article, we will discuss when the input logic is driven low (indicated by input voltage low (VIL)) and when it is driven high (indicated by input logic level high (VIH)). We will focus on analyzing VIH, the threshold uncertainty area marked as "Avoid" in Figure 2.

In all cases, a ±10% power supply tolerance must be considered. Figure 3 shows high-speed differential signaling. This article will focus on the standard logic levels shown in Figure 2.

Switching noise

When not adequately filtered, a switching regulator buck or boost power supply design can generate switching noise ranging from tens to hundreds of millivolts, with spikes that can reach 400 mV to 600 mV. Therefore, it is important to understand whether the switching noise will cause problems for the logic levels and interfaces used.

Safety margin

To ensure a suitable safety margin for a reliable PSU, a design rule of thumb is to use a worst-case tolerance of –10%. For example, for 5 V TTL, a VIL of 0.8 V becomes 0.72 V, and for 1.8 V CMOS, a VIL of 0.63 V becomes 0.57 V, and the threshold voltage (VTH) is reduced accordingly (5 V TTL VTH = 1.35 V, 1.8 V CMOS VTH = 0.81 V). The switching noise (VNS) can be tens of millivolts to hundreds of millivolts. In addition, the logic circuit itself also generates signal noise (VN), which is interference noise. The total noise voltage (VTN = VN + VNS) can be between 100 mV and 800 mV. VTN is added to the nominal signal to generate the total signal voltage (VTSIG): The actual total signal (VTSIG = VSIG + VTN) affects the threshold voltage (VTH), further expanding the avoid area. The signal levels in the VTH region are uncertain, and logic circuits can flip randomly within this region; for example, in the worst case, they can erroneously trigger a logic 1 instead of a logic 0.

Multi-Rail PSU Notes and Tips

By understanding the threshold levels of both the interface inputs and the IC’s internal logic, we now know which levels trigger the correct logic level and which (accidentally) trigger the wrong logic level. The question is: what level of noise performance does the power supply need to meet these thresholds? Low-dropout linear regulators are very low noise, but are not necessarily efficient at high voltage step-down ratios. Switching regulators can effectively step down the voltage, but they generate some noise. An efficient and low-noise power supply system should include a combination of both types of power supplies. This article focuses on various combinations, including a hybrid approach with an LDO regulator following a switching regulator.

Methods to maximize efficiency and minimize noise (when necessary)1, 2

From the design example shown in Figure 1, it can be seen that in order to maximize the efficiency of the 5 V regulation and minimize the switching noise, it is necessary to tap off the 12 V circuit and use a buck regulator, such as the ADP2386 from Analog Devices. From the perspective of standard logic interface levels, the 5 V TTL VIL and 5 V CMOS VIL are 0.8 V and 1.5 V, respectively, which also provide appropriate margin when using only switching regulators. For these rails, efficiency is maximized by using a buck topology, while switching noise is lower than the VIL when using 5 V (TTL and CMOS) technology. By using a buck regulator, such as the ADP2386 configuration shown in Figure 4a, efficiencies as high as 95% can be achieved, as shown in the typical circuit and efficiency graph of the ADP2386 (see Figure 4b). If a lower noise LDO regulator is used in this design, the 7 V drop from VIN to VOUT will result in a significant amount of internal power dissipated, which generally appears as heat generation and loss of efficiency. For a reliable design at a small additional cost, it is also an added advantage to use an LDO regulator after the buck regulator to generate the 5 V voltage.

The VIL of 2.5 V and 1.8 V CMOS is 0.7 V and 0.63 V, respectively. Unfortunately, this logic level does not have enough safety margin to avoid switching noise. To solve this problem, there are two options. First: If the external 3.3 V supply shown in Figure 1 has enough power and very low noise, tap this external 3.3 V supply and use linear regulators (LDO regulators) such as the ADP125 (Figure 5) or ADP1740 to obtain the 2.5 V and 1.8 V supplies. Note that there is a 1.5 V voltage drop from 3.3 V to 1.8 V. If this voltage drop causes problems, a hybrid approach can be used. Second: If the external 3.3 V supply is not low noise or does not provide enough power, tap the 12 V supply and generate the 3.3 V, 2.5 V, and 1.8 V supplies through a buck regulator followed by an LDO regulator; the hybrid approach is shown in Figure 6.

Adding an LDO regulator slightly increases cost and board area, as well as a small amount of heat sinking, but these trade-offs are necessary to achieve a safety margin. Using an LDO regulator will slightly reduce efficiency, but this efficiency reduction can be minimized by maintaining a small voltage drop from VIN to VOUT: 3.3 V to 2.5 V, maintaining 0.8 V, or 3.3 V to 1.8 V, maintaining 1.5 V. Regulators with VIOC can be used to maximize efficiency and transient performance. VIOC regulates the output of the upstream switching regulator to maintain a reasonable voltage drop across the LDO regulator. Regulators with VIOC include the LT3045, LT3042, and LT3070-1.

The LT3070-1 is a 5 A, low noise, programmable output, 85 mV low dropout linear regulator from Analog Devices. If an LDO regulator must be used, there is a heat dissipation issue, where power dissipation = VDROP × I. For example, the LT3070-1 supports 3 A, and the power drop (or power dissipation) across the regulator is typically 3 A × 85 mV = 255 mW. Compared to some typical LDO regulators with a dropout voltage of 400 mV, an output current of the same 3 A, and a power dissipation of 1.2 W, the LT3070-1 consumes only one-fifth of the power.

Alternatively, we can use a hybrid approach to improve efficiency at the expense of cost. In Figure 6, both efficiency and performance are optimized, where a buck regulator (ADP2386) is used first to step down the voltage to the lowest allowed voltage, maximizing efficiency, followed by an LDO regulator (ADP1740).

Figure 6. Hybrid topology using the ADP2386 and ADP1740 combination

Figure 7. ADP5054 single-chip multi-rail power solution for FPGA applications

1 This exercise provides a generic design example to show some topologies and techniques. However, don’t forget to consider other factors such as IMAX, cost, packaging, voltage drop, etc.

2 Low noise buck and boost regulator options are also available, such as Silent Switcher regulators, which offer extremely low noise and low EMI. For example, the LT8650S and LTC3310S are cost-effective in terms of performance, package, size, and layout area.

Packaging, power, cost, efficiency, and performance trade-offs

Production PCB designs often require compact multi-rail power supplies that achieve high power, high efficiency, excellent performance, and low noise. For example, the ADP5054 quad-step-down regulator provides a high power (17 A) single-chip multi-rail power solution for applications such as FPGAs, as shown in Figure 7. The entire power solution is approximately 41 mm × 20 mm in size. The ADP5054 itself is only 7 mm × 7 mm in size and can provide 17 A total current. To achieve extremely high power levels in a compact space, consider using ADI's Module regulators, such as the LTM4700, which can provide up to 100 A in a 15 mm × 22 mm package size.

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