GPIO internal structure and working principle

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GPIO internal structure and working principle [Copy link]

1. Introduction to STM32F103ZET6

1. STM32 physical picture:

　　

2. STM32 pinout diagram:

　　

STM32F103ZET6: 144 pins in total, 7 groups of IO ports, 16 IO ports in each group

7*16=112 IO ports (these 7 groups of IO ports are GPIOA, GPIOB...GPIOG)

For example: PGIOA includes PA0, PA1, PA2…PA15, each group has 16 IO ports

　

2. Basic structure and working mode of IO port

1. Basic structure of STM32F1 series IO port () Internal circuit structure of IO port)

　　

The I/O pins on the right are the pins exposed to the outside of the chip.

Each pin has instructions in the data sheet whether it supports (recognizes) 5V voltage

　

3. 8 working modes of GPIO

• 4 input modes

• Input floating

• Input pull-up

• Input Dropdown

• Analog Input

• 4 output modes

• Open-drain output

• Open-drain multiplexing function

• Push-pull output

• Push-pull multiplexing function

• Configurable 3 maximum flip speeds

• 2MHz

• 10MHz

• 50MHz

　

Four, eight working methods explained

1. GPIO input working mode 1-input floating mode

　　

1) External input level through IO port, external level through the pull-up and pull-down parts (both are closed in floating mode, there is no pull-up or pull-down resistor)

2) Transmitted to the Schmitt trigger (the Schmitt trigger is in the open state at this time)

3) Continue to transfer to the input data register IDR

4) The CPU reads the external input level value by reading the input data register IDR

In input floating mode, external input level can be read

　

2. GPIO input working mode 2-input pull-up mode　

Compared with the input floating mode, the difference is that there is an internal pull-up resistor connected to VDD (in the input pull-up mode, the pull-up resistor switch is turned on, and the resistance is about 30-50K)

External input passes through the pull-up resistor and the Schmitt trigger is stored in the input data register IDR and read by the CPU

　

3. GPIO input working mode 3-input pull-down mode　

Compared with the input floating mode, the difference is that there is an internal pull-down resistor connected to VSS (in the input pull-down mode, the pull-down resistor switch is turned on, and the resistance value is about 30-50K)

The external input passes through the pull-down resistor and the Schmitt trigger is stored in the input data register IDR and read by the CPU.

　

4, GPIO input working mode 4-input analog mode　

　

Both the pull-up and pull-down parts are in the off state (AD conversion - analog quantity converted to digital quantity)

Schmitt trigger is in cut-off state

Input to CPU through analog input channel

The external voltage of the IO port is an analog quantity (voltage form, not level form), and the analog input range is generally 0~3.3V

　

5. GPIO output working mode 1-open drain output mode

1.CPU writes bit set/clear register BSRR, mapped to output data register ODR

2. Connect to the output control circuit (that is, the level of ODR)

3. The ODR level enters the N-MOS tube through the output control circuit

• ODR output 1:

　　N-MOS is cut off, the IO port level is not determined by the ODR output, but by the external pull-up/pull-down

　　In the output state, the output level can be read, the data is stored in the input data register, and read by the CPU to realize the CPU reading the output level

　　Therefore, when the N-MOS is turned off, if the output level is read as 1, it is not necessarily the 1 we output, but may be the 1 generated by the external pull-up.

• ODR output 0:

　　N-MOS is turned on, and the IO port level is pulled down to VSS by the N-MOS tube, making the IO output low level

　　The low level output at this time can also be read by the CPU

6. GPIO output working mode 2-open drain multiplexing output mode　

The only difference from the open-drain output mode is the source of the level before the output control circuit

The output level of the open-drain output mode is controlled by the CPU writing to the output data register

The output level of the open-drain push-pull output mode is determined by the multiplexed function peripheral output

Others are similar to open-drain output mode:

The control circuit output is 1: N-MOS is cut off, and the IO port level is determined by external pull-up/pull-down

The control circuit output is 0: N-MOS is turned on, and the IO port outputs a low level

　

7, GPIO output working mode 3-push-pull output mode

Compared with open-drain output:

The output control register part is the same

The output driver part adds a P-MOS tube part

When the output control circuit outputs 1:

The P-MOS tube is turned on and the N-MOS tube is turned off, and it is pulled up to a high level. The IO port outputs a high level 1

When the output control circuit outputs 0:

The P-MOS tube is turned off and the N-MOS tube is turned on, which is pulled down to a low level. The IO port outputs a low level 0

At the same time, the output level of the IO port can be read through the input circuit

　

8, GPIO output working mode 4-multiplexed push-pull output mode

The only difference from the push-pull output mode is the source of the level before the output control circuit

The output level of the open-drain output mode is controlled by the CPU writing to the output data register

The output level of the open-drain push-pull output mode is determined by the multiplexed function peripheral output

　

9. The difference between push-pull output and open-drain output:

Push-pull output:

Can output strong high/strong low level, can connect digital devices

Open-drain output:

It can only output a strong low level (the high level needs to be pulled up by an external pull-up electronics), suitable for current type driving, and has a strong current absorption capability (within 20ma)

　

5. STM32-IO port related registers

Each GPIO group contains a series of 7 registers (7 groups of GPIO contain a total of 7*7=49 registers)

Two 32-bit configuration registers

GPIOx_CRL lower 16 bits

GPIOx_CRH high 16 bits

Two 32-bit data registers

GPIOx_IDR Input Data Register

GPIOx_ODR Output Data Register

One 32-bit set/reset register

GPIOx_BSRR

A 16-bit reset register

GPIOx_BRR

One 32-bit lock register

GPIOx_LCKR

6. Explanation of STM32-IO port related registers

1. Port configuration register:

Each GPIO group of STM32 has 16 IO ports, and each 4 bits controls one IO port, so 32 bits control 8 IO ports.

Divided into lower 16 bits: GPIOx_CRL and upper 16 bits: GPIOx_CRH, a total of 32 bits to control a group of 16 GPIO IO ports

　　

As shown in the figure: Taking the lower 16 bits of the port configuration register as an example, every four bits control one IO port (the same applies to the upper 16 bits)

MODEx 2 bits: configure IO port output/output mode (1 output + 3 output modes with different speeds)

CNFx bit 2: configure the input/output mode of the IO port in the input/output state (controlled by MODEx)

　

Taking GPIOA_CRL as an example, configure IO port PA0 -> MODE0=00 (input mode) CNF0=10 (pull-up/pull-down input mode).
In this configuration, whether the pull-up or pull-down input mode is still determined by the ODR register.　

Regarding the pull-up/pull-down control, we will explain it in detail when introducing the ODR output register in the following section - Data Register.

　

2. Data register (taking input data register GPIOx_IDR as an example)

Each group of IO ports has a 32-bit register GPIOx_IDR (actually only the lower 16 bits are used, and the upper 16 bits are reserved), that is, 16 bits control 16 IO ports, and each bit controls one

　　

As shown in the figure: The IDR register has a total of 32 bits, and bits 0 to 15 represent the current values of 16 IO ports of a group of IO ports.

　　

Here we have learned about the input/output data registers, now let's talk about the above-mentioned problems:

When the IO port is configured as input mode and configured as pull-up/pull-down input mode (i.e. MODEx=00 CNFx=10), ODR determines whether it is pull-up or pull-down.

1) When in output mode, ODR is the output data register

2) When in input mode, ODR is used to distinguish whether the current bit input mode is pull-up input (ODRx=0) or pull-down input (ODRx=1)

3. Port bit set/clear register (GPIOx_BSRR)

　　

BSRR register function:

The BSRR register is a 32-bit register. The lower 16 bits BSx are set (1 sets 0 unchanged), and the upper 16 bits BRx are reset bits (1: clear 0: unchanged)

Of course, the ultimate goal is to indirectly set the ODR register through BSRR and change the IO port level.

　

4. Port bit clear register (GPIOx_BRR)

　　

The function of the GPIOx_BRR register is the same as the high 16 bits of the GPIOx_BSRR register

Generally, we use the lower 16 bits of BSRR and the lower 16 bits of BRR (the STM32F4 series cancels the upper 16 bits of BSRR)

　

5. Latch register: seldom used, not analyzed for now

　

7. Port multiplexing and remapping

1.Port multiplexing:

Most IO ports can be reused as external function pins, refer to the chip data sheet (IO port multiplexing and remapping)

　　

For example, the PA9 and PA10 pins of STM32F103ZET6 can be multiplexed as serial port send and receive function pins, and can also be multiplexed as channel 2 and channel 3 of timer 1.

The role of port reuse: maximize the use of port resources

　

2. Port remapping:

　　

The default pins of serial port 1 are PA9 and PA10, which can be remapped to PB6 and PB7 through configuration.

The role of port remapping: convenient wiring

　

3. All IO ports of STM32 can be used as interrupt input (51 MCU only has 2 ports that can be used as external interrupt input)

The above is the working principle of STM32-GPIO and the contents of related registers

- --Porter

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