Author | Jiang Jie (Member of the YiBo Technology Expressway Team)
Routing is busy, deadlines are tight; routing is busy, filing is urgent.
At the beginning of the project, Mr. Gaosuo was actually resistant because he really didn't see the need for simulation: the target signal was DDR3L, the data rate was up to 800Mbps, and the address control signal routing topology was one-to-two, T-type topology. The signal was ordinary, the rate was ordinary, and the topology was simple.
Unable to withstand the customer's repeated insistence, and in the early stage of project intervention, the customer was evasive and not very forthcoming when providing PCB files, as if there was something to hide, Mr. Gaosuo gradually became alert - things might not be as simple as imagined. The customer finally provided the single board file, but kept emphasizing that it was designed by an outsourcing company.
After opening the board and taking a closer look, it was full of dangers. Mr. Gaosuo was refreshed and had a rough idea in his mind. Although he had made a prediction, he had only heard of such an unusual design before, and when he saw it today, he was inevitably excited and really wanted to see if the simulation results were consistent with expectations.
Considering selecting address control signals as the simulation object, the reason for doing so is not only because the wiring of such signals on this single board is radical, but also because compared with the point-to-point topology of most data signals, address control signals are usually one-to-many, and there is no on-chip termination corresponding to the data signal to reduce reflection, so the probability of problems is relatively high. Let’s first look at the longest signal waveform of the DDR3L address control line (as shown below): the high and low levels are distinct, meeting the threshold requirements, the edges are monotonous, and there is no return groove. Although there is slight overshoot and ringing overall, it is not perfect, but it is relatively normal.
Is this a happy PASS? No, it's not the point yet. Because the result of the overall channel simulation will lead you to a completely opposite conclusion! If you don't believe it, please look at the bleak eye diagram when the same group of address signals are running simultaneously: it's like eyes that are barely opened after staying up late, full of bloodshot. Do you feel his fatigue?
Sorry, I put the wrong picture, it should be this one.
The quality of a single signal is fine, but the same group of signals is not good when running together. I believe that friends who have been following Mr. Gao's official account have already thought of the answer: crosstalk! Yes, Mr. Gao thinks so too. Especially after Mr. Gao recently launched a short video about inter-layer crosstalk, the crosstalk problem has attracted the attention of many people. For more information, please click the following link:
https://www.bilibili.com/video/BV13Q4y1N7yW
Back to this case, let’s continue to unravel the mystery. A careful look at the spacing between the DDR3L address signal traces reveals a clue: the trace width is 0.1mm, and the air-gap between adjacent traces is also 0.1mm! And this is not just a sporadic phenomenon, the address control signals of the entire channel are processed in this way.
Of course, the above inferences about crosstalk are only bold assumptions, and the following needs to be carefully verified. Since it is suspected that the crux of the problem lies in crosstalk, then comparing the impact of different degrees of crosstalk on channel signals is the most convincing. Fortunately, the crosstalk coefficient can be adjusted during simulation, so there is no need to wait for customers to provide different PCB versions for verification one by one. When extracting parameters, by adjusting the crosstalk coefficient, first reduce the crosstalk to 75% of the original version. Due to the reduction of ringing, the "bloodshot" in the eyes begins to decrease, and the eye diagram is as follows:
The crosstalk coefficient was further adjusted to reduce the crosstalk to 50% of the original design. The signal ringing was further reduced and the eye diagram gradually returned to normal.
Directly reducing the crosstalk to 5% of the original design, the entire eye diagram becomes energetic and very refreshing.
Through simulation feedback, the customer finally adjusted the DDR3L routing center distance to 3W. The channel simulation results after the adjustment of the line distance met the expected requirements.
Later, I learned that the initial version of the PCB was designed by a novice Layout designer. The newborn calf was not afraid of the tiger, and the pressure of delivery date led to deviations in the routing constraint settings, so a design that tested the signal bottom line appeared. I believe that after this torment of rework, crosstalk will no longer be a pale theory in books for this Layout engineer. As the saying goes: routing is busy, and delivery date is urgent; routing is busy, and crosstalk soars. However, how many routings can be repeated, and how many boards can withstand the wait?
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