Counting TI's star products in T-BOX: linear regulators | Section 5: TPS7B7701-Q1: Safeguarding automotive applications

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Counting TI's star products in T-BOX: linear regulators | Section 5: TPS7B7701-Q1: Safeguarding automotive applications [Copy link]

 

New hot spots in automobiles: TI's star products in T-BOX (in progress)
Interface	PHY	Section 1 DP83TC811S-Q1: Automotive Ethernet makes your T-BOX even more powerful
	CAN	Section 2 TCAN1042-Q1: “Hard-core” CAN transceiver
Power	Wide Vin BUCK	Section 3 LMR33630-Q1: An excellent choice for primary power supply
	Low Vin BUCK	Section 4 TPS6281x-Q1: A “seed player” for secondary power supply
	LDO	Section 5 TPS7B7701-Q1: Safeguarding Automotive Applications
…	…	…
New hotspot in automobiles: In-depth analysis of T-BOX system solutions (completed)
Section 1		Power Rails
Section 2		Charge and discharge management
Section 3		interface
Section 4		Emergency call unit
Section 5		Wireless connection unit

Section 5 TPS7B7701-Q1: Safeguarding Automotive Applications

Compared with the BUCK mentioned in the previous two sections, in the automotive field, the low dropout linear regulator (LDO) has good voltage ripple suppression and electromagnetic compatibility (EMC) performance, and is also one of the most popular electronic power supplies in automotive applications.

This article will introduce various specifications of LDO in automotive applications (such as T-BOX), such as parameters, characteristics and automotive standards that need to be met, with a focus on battery DC systems and non-vehicle board-level load systems. In addition, it will introduce TI's LDO star product in automotive applications (such as T-BOX), TPS7B7701-Q1, and other excellent partners.

The LDO can be powered by the system battery or the front-end power supply. The requirements for LDOs directly connected to the battery are more stringent: it must pass the ISO 7637 standard of the International Organization for Standardization and be able to withstand load dump. During operation, the LDO can power the target load through the PCB traces in the vehicle system or the cables in the non-vehicle system board-level system. For non-vehicle board-level systems, the LDO must protect itself from various potential cable faults.

In current automotive designs, a 12 V battery is usually used to power the system. A stable low-voltage power supply is required for system operation, but changing loads and other environmental factors can cause the 12 V power supply to vary. LDOs are directly connected to the car battery to convert harsh high voltages into stable low-voltage outputs. Most LDOs output 3.3 V or 5 V, or the output is configurable. Compared with BUCKs, LDOs are simple and easy to use; an output capacitor ensures the stability of the device. At the same time, passing EMC tests is not difficult because the topology of the LDO does not generate any switching noise.

Internal topology

LDO is a negative feedback control system consisting of a signal sampling circuit, a signal processing circuit, and a power control circuit. The resistor divider samples the output voltage and then compares it with a precise internal reference voltage. The difference between the two signals represents the offset of the output voltage relative to the target value. The system uses this difference to control the field effect transistor (FET), which is usually low RDS(on), to control the output value. To ensure system stability, LDO has the necessary compensation circuit, as shown in Figure 1.

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Figure 1 Internal topology of LDO

Adjustable output voltage

As shown in Figure 2, when feedback (FB) is present, the output voltage of the LDO can be adjusted by external resistor divider. The output voltage is calculated by the following formula:

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Where V(FB) is the internal reference voltage, R1 is the resistor connected between OUT and FB, and R2 is the resistor connected between FB and GND.

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Figure-2 LDO adjustable output application circuit

Car battery voltage characteristics

Currently, cars mainly use 12 V batteries, while trucks and heavy vehicles use 24 V batteries. In actual applications, the alternator driven by the engine charges the battery. If the battery is disconnected due to cable corrosion, poor contact or disconnection while the engine is running, load dump may occur. According to the ISO 7637-2 standard test pulse 5a, the maximum transient voltage of the battery can be as high as 99 V in a 12 V system and 198 V in a 24 V system, lasting about hundreds of milliseconds. See Figure 3 and Table 1 for details (from the ISO 7637-2-2004 standard).

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Figure 3 ISO 7637-2 Load Dump Test Pulse A	Table-1 ISO 7637-2 Load Dump Test Pulse A

In most new alternators, a diode is added to suppress the magnitude of the load dump. A suppression circuit is usually placed in front of the input of the LDO, as shown in Figure 4.

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Figure-4 Car battery voltage suppression circuit

An example of a real load dump voltage at the input of the LDO is shown in Figure 5. The specified suppression voltage is (Ua + 0.1Us + Us*). In a 12V system, the battery voltage is usually limited to less than 40V.

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Figure 5 ISO 7637-2 Suppression of battery voltage

DC parameters

1) Quiescent current

Quiescent current is the current difference between the input and output, which is the current consumed by the LDO itself. Quiescent current is critical for always-on applications such as immobilizer systems. During the key-off state, the immobilizer system still operates in standby mode and consumes battery energy. Therefore, low quiescent current can extend battery life.

Bipolar transistor and BCD (Bipolar/CMOS/DMOS) technology are two common LDO topologies. It is difficult to achieve low quiescent current using bipolar topology. Figure 6 is a PNP transistor LDO topology. Some current flows into the base of the transistor, which causes energy loss. NPN transistor LDO requires a charge pump, which causes additional quiescent current. For LDOs with BCD topology, since MOSFET is a voltage-controlled device, there is no base leakage current. No current flows into the gate of the pass element. Therefore, the quiescent current can be much lower. Figure 7 is an LDO with a PMOS structure.

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Figure-6 PNP transistor LDO	Figure 7 PMOSFET LDO

2) Pressure difference

Under normal LDO operating conditions, the input voltage must be higher than the output voltage by a minimum value. This increment is defined as the dropout voltage. In dropout mode, the power FET of the LDO operates in the linear region. The output voltage can be calculated from the following formula, where RDS(on) represents the on-resistance of the power FET.

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In automotive applications, low dropout is important during startup conditions when the battery voltage drops to 6V. To maintain a 5V output to the MCU, as shown in Figure 8, the dropout voltage of the LDO plus the forward voltage of the reverse blocking diode needs to be less than 1V. There are many low dropout LDOs in TI's high-voltage LDO portfolio. For example, the TPS7B6750-Q1 has a dropout voltage of only 280mV at 450mA load at room temperature. To guarantee a 5V stable output at 450mA load, the input voltage must be above 5.28V. With such a low dropout voltage, the device can operate over a wider input voltage.

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Figure-8 Simplified application diagram of car battery directly connected to LDO

3) Temperature range

For devices for automotive applications (including LDOs), data sheets usually specify the operating ambient temperature range. According to the Automotive Electronics Council (AEC) Q-100 standard, there are four grades (0, 1, 2, and 3) as shown in Table 2.

• Grade 0 is the highest grade. Devices in this grade can operate at 150°C. Grade 0 devices are typically used in very harsh automotive environments, such as powertrain systems.
• Grade 1 devices are the most common grade of devices found in automotive systems.
• Level 2 devices are designed to meet certain requirements where system safety is less critical, such as infotainment systems.
• Level 3 is not popular in automotive applications because the ambient temperature in an empty car is often above 85C.

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Table - 2 AEC Q-100 temperature grades 0, 1, 2 and 3

characteristic

1) POWER GOOD

To ensure the system is normal, the MCU power supply must be ready before taking any further action. This requirement requires the LDO driving the MCU to have a POWER GOOD function, as shown in Figure 9.

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Figure-9 LDO POWER GOOD application circuit

2) Output voltage undervoltage reset

Output voltage undervoltage reset (OVUVR) is a self-check function of the LDO. The system must confirm that the MCU is powered correctly to avoid logic errors. The LDO uses OVUVR to check this power supply.

As shown in Figure 10, the LDO continuously monitors its output and once the output voltage drops below an internal threshold, the LDO self-diagnoses its root cause. After eliminating the system noise effect, the LDO resets the MCU.

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Figure-10 LDO low voltage reset

3) Power-on reset delay

MCU requires a suitable supply voltage and an accurate timing reference. LDO can ensure timing through the power-on reset function. In most cases, the MCU timing reference comes from a crystal oscillator. After power-on, the MCU needs 1-10 ms to stabilize and generate an accurate timing clock. During the crystal oscillator stabilization process, the MCU must be kept in reset. Current LDOs provide a power-on reset delay function. Figure 11 details the logic flow of this function. The LDO first provides a stable output voltage to the system and only turns off the POWER GOOD signal after a preset delay. This function can help the MCU's internal crystal oscillator power up before fully enabling the MCU.

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Figure 11 LDO power-on reset behavior

4) Power-on reset delay time

An additional delay pin is required to adjust the power-on reset delay time. The timer delay can be set by an external capacitor on the delay pin before POWER GOOD is high. The constant output current I(CHG) charges the external capacitor C(DELAY) until the voltage on the delay pin exceeds the threshold V(TH) to trigger the internal comparator.

The power-on reset delay time t(POR) is defined by the charging time of C(DELAY) on the delay pin, as shown in the following equation:

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Assume that the LDO has the power-on reset parameters shown in Table 3.

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Table - 3 Power-on reset parameter example

After connecting a 100nF capacitor to the delay pin, the power-on reset delay time calculated by the formula is:

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5) Watchdog Timer

The watchdog timer is an important function in the system. Since people cannot always monitor the system with safety as the top priority, the watchdog timer function can always monitor the operation of the MCU and verify its normal operation. In Figure 12, the LDO provides watchdog service for the MCU. Under normal circumstances, the MCU will "feed the dog" regularly. If it is not "fed" regularly, the MCU is in an abnormal state. In this case, the watchdog timer resets the MCU to a known state and forces a new logic sequence.

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Figure-12 LDO watchdog timer application diagram

For MCUs that use an internal watchdog, reliability is not enough. Runaway software could reprogram the internal watchdog timer controller. A good watchdog should be independent of the MCU it is trying to protect.

There are two types of LDOs with integrated watchdog timers: standard timers and window timers. Figures 13 and 14 show the difference between the two. An MCU may get stuck in a routine that emits pulses at a higher frequency than its normal state. A standard watchdog cannot detect this potential error and therefore interprets the signal as valid.

To solve this problem, a more advanced watchdog, called a window watchdog timer, monitors both the minimum and maximum pulse periods. If a watchdog pulse does not occur within a certain time frame, the window watchdog will reset the MCU.

Figure 14 is a flow chart of the window watchdog timer. To prevent the watchdog timer from sending a fault signal during the open window or watchdog initialization state, a rising edge must be generated on the WD pin. No service signal should be received in the closed window because the watchdog timer is being programmed through the resistor on the corresponding pin.

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Figure - 13 Window monitoring timer sequence diagram	Figure - 14 Window monitoring timer flow chart

6) Enable signal

In battery-powered applications, including LDOs connected directly to the car battery, efficiency is critical. In non-operating modes, system modules often reduce their power consumption to very low levels. As shown in Figure 15, driving the enable (EN) pin low saves LDO power. When the system needs to be powered up, the LDO can be woken up by driving the EN pin high.

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Figure-15 LDO Enable Application Diagram

7) Forewarning

Before power is removed, the system must take steps to store critical information into the EEPROM. Normally, the MCU controls the power-off sequence and has enough time to follow the correct sequence, but in some cases, peripheral resistance causes power-off and the LDO must send an early warning of the impending power drop to the MCU, giving the MCU time to store data. Figure 16 shows an example of a typical LDO application with early warning capabilities.

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Figure-16 LDO early warning application diagram

The early warning function monitors the input voltage by comparing the divided input voltage with the internal reference voltage. Figure 17 shows the early warning function when the voltage on the SI pin drops below the detection low threshold. The detection output pin generates an active low signal. When the voltage on the SI pin rises above the detection high threshold, the detection output pin generates an active high signal.

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Figure-17 Warning Behavior

To set the threshold voltage to trigger the early warning, the ratio of the external resistor divider can be calculated using the following formula:

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Protect

1) Current Limiting and Thermal Shutdown

In automotive applications, safety and reliability are always top priorities. It is important for the LDO to protect itself under fault conditions. The most likely system failure is an output short to GND, which can be caused by a connector short or soldering problem. To prevent the output from being shorted to GND and causing damage to the LDO, current limiting and thermal shutdown protections are necessary. Figure 18 shows a typical block diagram of an LDO with current limiting and thermal shutdown protections. The closed loop implements current limiting and compares the output current of the regulator with an internal current reference. When the output current exceeds the current limit, the voltage difference Vgs between the gate and source of the PMOS is clamped at a certain level, which limits the current flowing through the pass element.

A short to ground will trigger the current limit. Due to the high voltage drop and current flow, a lot of heat will build up across the regulator, so the junction temperature will increase and can damage the device, which is why thermal shutdown protection is critical. The device will shut down when the junction temperature rises above the thermal shutdown threshold, which is typically 175C for automotive grade 1 devices. Although this is a typical value, other devices may have different trip points. After cooling, the device automatically restarts with a typical hysteresis of 15C, as shown in Figure 19.

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Figure-18 LDO current limit and thermal shutdown internal circuit	Figure-19 Thermal shutdown behavior

2) Reverse polarity protection

There are several possible scenarios that could lead to a reverse polarity condition:

• When the output voltage is higher than the input voltage.
• When the input is turned on while a positive output voltage is applied.
• When the input voltage is negative and the output has a path to ground.

Figure 20 is an example of reverse polarity. The current may flow into the GND pin or the output pin of the regulator. Different types of protection are required for different components and device circuit architectures.

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Figure-20 LDO reverse battery connection

Having a single MOSFET transistor through an LDO (both NMOS and PMOS) does not provide reverse polarity protection, as shown in Figure 21-22. Reverse current may flow through the body diode of the MOS under reverse polarity conditions. The reverse current is not limited and may cause device damage. Therefore, a series diode is required at the device input. The voltage drop of the series diode must also be considered. It is best to use a Schottky diode with a low forward voltage.

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Figure 21 LDO internal current under reverse polarity (NMOS)	Figure - 22 LDO internal current under reverse polarity (PMOS)

A negative supply voltage can be applied to the regulator with a PNP transistor. The PNP transistor limits the reverse current under reverse polarity conditions; therefore, a reverse protection diode is not required at the input. Figure 23 shows the internal block diagram of the TLE4275-Q1 , which is designed with a PNP bipolar architecture.

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Figure-23 Internal block diagram of a bipolar LDO (PNP transistor).

Reverse polarity protection is a must-have feature for onboard load power LDOs. Long cables are used to connect the LDO output and external loads. In harsh automotive environments, the cables are likely to break or even short to the battery. In this case, reverse polarity occurs if the LDO input is connected to a voltage rail (such as a BUCK output) that is lower than the battery voltage.

A regulator with back-to-back MOSFET topology senses the output voltage under reverse polarity conditions. If the output voltage is higher than the input voltage, both MOSFETs are turned off immediately. The body diode of the PMOS is close to the input of the regulator, so reverse current is blocked. Figure 24 shows the internal block diagram of this LDO.

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Figure-24 Back-to-back MOSFET LDO internal block diagram

3) Inductive load clamping

Inductive load clamp protection is critical for powering inductive loads, such as an antenna LDO with an LC filter connected to the output, or if a trace LDO with long cables is used with parasitic inductance connected to the output.

When the LDO is powered down, if the load is inductive, a negative voltage will appear on the output because the inductor resists the change in current. Figure 25 shows a typical example of LC oscillation during power down. If the negative voltage exceeds the absolute minimum voltage of the regulator output pin (such as -0.3V), damage may occur.

Adding a diode between the output of the LDO and GND can clamp the negative voltage to a certain voltage, such as -0.3 V. Some LDOs implement a blocking diode in their structure to save system design work, as shown in Figure 26.

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Figure-25 Inductive load power-off behavior	Figure-26 Internal inductor clamping diode at LDO OUT

Application Selection

1) Capacitor

There are three types of capacitors commonly used in automotive systems:

• Ceramic capacitor: has a smaller package and lower electrostatic resistance (ESR) (on the order of tens of milliohms); however, it does not provide larger capacitance or withstand higher working voltages.
• Aluminum electrolytic capacitors: large capacitance, can withstand higher operating voltage, but poor ESR performance. When the temperature drops, the ESR may rise to more than 10 ohms
• Tantalum capacitors: ESR characteristics are both stable and accurate over their service life, but they are also more expensive.

2) Input Capacitor

In a 12 V automotive system, the voltage on the power rail can spike to quite high levels. As mentioned earlier, the abnormal voltage is usually clamped to less than 40 V, depending on the transient voltage suppression (TVS) diodes applied.

Some automotive systems need to meet the requirements of cold crank condition testing to operate under low input voltage stress for a certain period of time. In this case, a larger input capacitor helps absorb and store energy. Aluminum electrolytic capacitors have a high voltage range and large capacitance. Since the input capacitor has no effect on the loop response of the LDO, its poor equivalent series resistance (ESR) performance is no longer a problem.

3) Output capacitor

As mentioned before, LDO is a negative feedback system. It needs to properly handle poles and zeros to maintain system stability. The capacitance and ESR of the output capacitor form the zero, as shown in Figure 27.

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Figure-27 Output Capacitance and ESR

Figure 28 is a typical Bode plot of an LDO system. If the output capacitor has the correct ESR value, there will be two poles and one zero in the bandwidth, resulting in a stable system. If the ESR of the output capacitor is too large, the zero moves to a lower frequency and three poles appear in the bandwidth of the LDO, which can cause oscillation, as shown in Figure 29.

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Figure-28 LDO Stability Bode Plot	Figure 29 Bode plot of LDO instability with high ESR output capacitor

If the output capacitor ESR is too small, the zero will move towards higher frequencies beyond the LDO bandwidth, as shown in Figure 30, in which case the loop will also oscillate. In automotive systems, certain applications require specific capacitors. Supporting a wide range of ESR has become an important consideration in LDO design and selection. Figure 31 shows the stable region of an LDO when the correct output capacitor is selected, with an ESR between 1m ohm and 20 ohm and a capacitance between 10 uF and 500 uF.

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Figure-30 Bode plot of LDO instability with low ESR output capacitor	Figure-31 Output capacitance and ESR stability region (blue)

4) Load transient response

Load transient response describes the behavior of the LDO output during large load current changes, which are common in automotive systems. For example, too much overshoot of the LDO output may damage the MCU, while too much overshoot may cause erroneous logic. Load transient response affects control accuracy, especially when the analog-to-digital converter (ADC) uses the LDO output as a reference.

In order to obtain good load transient performance, a common approach is to increase the bandwidth of the LDO loop. Once a current step occurs, the loop will respond after a certain time Δt, which is proportional to the loop bandwidth f. The following equation represents this logic:

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As mentioned in the previous section, the LDO’s output capacitor ESR stability range is wide, making it easier to select capacitors; at the same time, the wide range results in a large zero point variation, which makes it difficult to stabilize a wideband loop. One solution is to implement a fast loop in the LDO system, as shown in Figure 32. The change in output voltage is directly reflected to the gate of the MOSFET. This approach has both good transient performance and a wide tolerance for capacitor ESR values.

Figure 33 shows the transient performance of a 47uF low ESR ceramic capacitor with an LDO implemented with a classic fast loop. A step change in load current (red trace) on the LDO drops the LDO output (light cyan trace) to 180 mV. After 60 us, the LDO starts to recover and eventually reaches a regulated output without any overshoot.

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Figure - 32 LDO fast loop internal block diagram	Figure-33 Single-channel LDO load transient response

Figure 34 shows the Bode plot of the fast loop IC above with a 200mA load. TR1 is the gain in decibels and TR2 is the phase in degrees. The bandwidth shown by TR1 is 1.627 kHz. Without the fast loop, the loop response time should be about 615us. With the fast loop, the response time is only 60us. The fast loop LDO combines good transient performance with a wide output capacitor ESR stability range (0.001-20 ohm).

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Figure - 34 Bode plot of a single channel LDO with 200 mA load and 47uF output capacitance

Junction Temperature and Thermal Characteristics

Most LDOs specify their maximum junction temperature to ensure normal operating conditions. Exceeding this limit may affect the reliability of the LDO, and it also limits the power dissipation of the LDO. To ensure that the junction temperature is within the acceptable range, the power dissipation must be lower than the maximum allowed value calculated using , where T(J_MAX) is the maximum allowed junction temperature, TA is the ambient temperature, and θJA is the ambient to junction thermal resistance specified in the data sheet.

查看详情In TI standard data sheets, the θJA value is usually simulated using the JESD51 2s2p PCB. Figure 35 shows the JESD51 2s2p PCB layers.

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Figure - 35 Cross section of a JEDEC JESD51 2s2p board	Table- 4 LDO thermal resistance example

Assuming that Table 4 shows the thermal resistance of the LDO chip, if the application condition is TA = 85°C, the maximum power dissipation can be calculated using the formula for the SOT-223 package:

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When using the JESD51 2s2p board, the power dissipation of this LDO must be less than 1.01 W to ensure that its junction temperature is below 150°C

Figure 36 shows an LDO with complete general functions including enable, POWER GOOD, adjustable output voltage, early warning, and watchdog timer.

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Figure - 36 General LDO application schematic diagram

Figure 37 provides the thermal rating of an LDO package connected directly to a battery.

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Figure 37 Thermal ratings of TI automotive packages

TI has a complete portfolio of LDOs for direct automotive-to-battery connections (see Figure 38). The LDOs in this product tree are categorized by output current, quiescent current, and functionality. Some are designed for specific applications. For example, the antenna LDO TPS7B770x-Q1 is used for automotive antenna power supplies. Table 5 lists the target applications for these specific LDOs.

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Figure-38 TI Automotive Direct-to-Battery LDO Selection Guide

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Figure-39 Dedicated LDO Selection Guide

LDO for T-BOX

In T-BOX applications, LDO may be used in several places: the power supply directly connected to the battery and the secondary power supply.

The most common power supply directly connected to the battery is to power the antenna and the CAN transceiver. These two applications have high voltage requirements, generally 40V. As mentioned repeatedly before, for LDO directly connected to the battery, in antenna applications, TPS7B7701-Q1 is a star product, which integrates diagnostic and protection functions; in CAN bus applications, the requirements for static power consumption are relatively high, and the TPS7B69-Q1 with a static current of 15uA is also a good choice. Of course, the TPS7B82-Q1 with a static current of only 3uA has better performance.

For example, the TPS7B7701-Q1 is AEC Q100 certified and has an output current of up to 300mA. It also has the following features:

• 4.5V to 40V wide input voltage range, 45V load dump protection.
• High-precision current sensing enables high-accuracy diagnostics without further calibration.
• Available in single and dual channel versions, pin compatible for easy scalability.
• It integrates diagnostic and protection functions, and integrates back-to-back MOSFET and freewheeling diode internally, saving system-level costs; it supports thermal shutdown, undervoltage lockout, short-circuit protection, reverse polarity protection, inductor clamping protection, etc.

The secondary power supply is mainly used to convert the voltage below 6V to 1.8V (or 2.5V/3.3V…), mainly for powering loads such as Ethernet, MCU, CODEC, etc. Different LDOs can be selected according to different current requirements, such as TLV700-Q1 (200mA), LP5907-Q1 (250mA), TLV702-Q1 (300mA) and LP5912-Q1 (500mA), etc. These are widely used products in T-BOX.

For example, the LP5912-Q1 is AEC Q100 certified and has an output current of up to 500mA. It also has the following features:

• Low noise (12Vrms @10-100kHz) and good PSRR (75dB, typ.) make it suitable for noise-sensitive applications.
• Low voltage drop (Vdo 95mV @ IL=500mA, Vout>3.3V) for highest efficiency and best thermal performance.
• The package is quite compact, 2x2mm WSON-6L.
• With thermal overload protection, short circuit protection and reverse current protection.
• No noise bypass capacitors are required.

In summary, in automotive applications such as T-BOX, whether it is in applications directly connected to the battery (TPS7B7701-Q1/ TPS7B69-Q1/ TPS7B82-Q1) or as a secondary power supply (TLV700-Q1/ LP5907-Q1/ TLV702-Q1 / LP5912-Q1), TI has excellent products to choose from, providing safer and more reliable protection for your in-vehicle applications and escorting your applications!

maychang

The two input terminals of the op amp in Figure 1 are drawn reversely.

maychang

In Figure 7, is that a P-channel MOS tube? Is it drawn wrong? The channel part should be reversed.