C6000 Fixed-Point DSP-C645x Application Guide

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C6000 Fixed-Point DSP-C645x Application Guide [Copy link]

C645x series high-performance fixed-point DSP, C645x series DSP is built on the latest enhanced C64x+ DSP core architecture, based on the third-generation very long instruction structure VelociTI.3. C645x series DSP is mainly aimed at various basic terminal equipment applications, including high-end telecommunications equipment, wireless basic terminal, video and imaging applications. C645x series DSP not only provides developers with twice the memory capacity and I/O bandwidth of TMS320C641x DSP, but also has other advanced features and functions, realizing the low-cost meeting of the new generation of systems for higher processing performance and larger memory capacity requirements.

C6000

C6000 ^TM Multi-core DSP + Arm SoC

The main features and advantages of the C645x series DSP:

◆ The memory capacity and I/O bandwidth are twice that of C641x, the main frequency is as high as 1.2G, the peak computing speed is 9600 MMACS (MIPS), and the price is basically the same as TMS320C6415 DSP.

◆ The enhanced C64x+ DSP core improves system performance by 20%, reduces code size by 20% to 30%, and achieves 100% code compatibility with the TMS320C64x DSP.

◆ The memory expansion interface adds support for high-performance, large-capacity DDR2 SDRAM.

◆ Serial RapidIO (SRIO) and Gigabit Ethernet MAC serializer/deserializer (SERDES) interfaces support efficient interconnect communications, enabling efficient inter-processor communications.

◆ 49 new instructions. Taking the multiplication unit as an example, the improvement and new instructions of this unit increase the multiplication operation bandwidth, support 32-bit multiplication and complex multiplication, and increase the number of 16×16 MACs per cycle to 8, which greatly improves the performance of DSP in processing DCT and FFT transformations.

◆ Added software pipeline cache (SPLOOP Buffer). The software pipeline of the original C64x core (used by C62x and C641x) further improves the processing performance of the DSP. It can not only overcome the impact of multi-cycle instruction delay on CPU processing performance, but also output one or more processing results in each cycle of the pipeline operation stage.

◆ Support compact instructions. The original C64x core only supports fixed-length instruction fetch packets, while the C64x+ core supports instruction fetch packets with a "header". The instruction packet header marks which of the other 7 words in the instruction packet are 32-bit opcodes and which are 16-bit opcodes. Supporting compact instructions can save program storage space and increase the hit rate of program cache.