Our company recruits outstanding fresh graduates from major universities. No experience is required, and the company provides paid internal training . Requirements : 1. Bachelor degree or above in electrical engineering. 2. Preference will be given to those with excellent academic performance. 3. CET-4 or above. 4. Interested in semiconductor design. 5. Willing to learn high-tech and enthusiastic about work. Training goals: Independently complete the floorplan & layout of the entire digital-analog hybrid chip, be able to perform various physical tests and parameter extraction such as LVS/DRC/Antenna/ERC/XRC, and ultimately achieve successful chip tape-out. This content was originally created by the EEWORLD forum user Floorplan Little Fairy . If you need to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source. In addition : The company has set up an IC layout training class, recruiting self-funded students from the society. 1. No restrictions on majors or academic qualifications 2. Age under 40 years old 3. IC designers who expect to get a high-paying offer 4. People who are interested in IC design
Trained by a senior director with 20 years of overseas experience, students can reach the level of professional engineers in the shortest possible time and independently complete the floorplan & layout of the entire digital-analog hybrid chip. If you are interested, please contact me at uic_hr@163.com WeChat ID: shouhappy
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