(Repost) CC2640R2F BLE5.0 CC2640R2F hardware architecture

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(Repost) CC2640R2F BLE5.0 CC2640R2F hardware architecture [Copy link]

Hardware Architecture

Overview

TI Bluetooth Low Energy Software Development Kit (ble-stackSDK) is a complete software platform for developing single-mode low-power Bluetooth applications. TheSDK is based on the complete system-on-chip (SoC) Bluetooth Low Energy solution SimpleLink CC2640R2F. The CC2640R2F combines a 2.4GHz RF transceiver, 128KB system programmable memory, 20KB SRAM, and a rich set of peripherals. It has an ARM Cortex-M3 series processor to handle applications and the Bluetooth low energy protocol stack, and an ARM Cortex-M0 processor to handle all low-level radio control and the associated physical layer and part of the link layer. The sensor controller module is capable of autonomous data acquisition and control independent of the Cortex-M3 processor, providing additional flexibility and further extending the low-power capabilities of the CC2640R2F. The following figure shows the module block diagram. For more information about CC2640R2F, see CC26xx Technical Reference Manual. 407620 Hardware Core As shown in the block diagram above, it is not difficult to see that CC2640R2F contains three physical cores. Each CPU can be used independently or share RAM/ROM. The three CPUs perform their respective duties and work together to achieve the greatest balance between performance and power consumption. The ARM Cortex M3 (Main CPU) system core (CM3) is designed to run the link layer of the Bluetooth low energy protocol stack to the user application. The link layer is connected to the radio core through a software module called the RF driver, which sits above the RF doorbell. The RF driver runs on the CM3 and acts as an interface to the radio on the CC2640R2F and also manages the power domains of the radio hardware and the core. For documentation on the RF driver, see the TI-RTOS Drivers Reference. The RF driver is the TI low-power Bluetooth protocol stack, which is implemented in the library code. The protocol stack and application both work on the M3 and its 128Flash. Be sure to distinguish them. We have mentioned the App+stack project management method above. The entire App+Stack runs on the CPU, not the wrong understanding that the App works on the M3 and the Stack protocol stack works on the M0. ARM Cortex M0 (RF Core) The Cortex M0 (CM0) core within the CC2640R2F is responsible for interfacing with the radio hardware and translating complex instructions from the Cortex M3 (CM3) core into data that can be sent over the radio. For the Bluetooth low energy protocol, the CM0 implements the physical layer (PHY) of the protocol stack. Typically, the CM0 is able to run autonomously, freeing up the CM3 to handle higher-level protocol and application layers. CM3 communicates with CM0 through a hardware interface called RF Doorbell, which is described in Section 23 of the CC26xx Technical Reference Manual.There are instructions in Section 2.

For the CM0 here, user programming is not provided, and it is solidified by TI before leaving the factory. M3 communicates with each other through register write command primitives and sharedRAM. For advanced protocol stacks such as BLE, the physical layer operation is almost shielded, so we almost don't need to care about CM0 here. For some private protocol development based on the physical layer(CC13x0), some design may be required.

SensorController

is a power-optimized 16-bit microcontroller with 2KSRAM, responsible for some peripheral control, ADC sampling, SPI communication, etc. When the system CPU is dormant, the SC can work independently. This design greatly reduces the system CPU wake-up frequency, thereby reducing power consumption.

and Cortex-M0, we do not need to care about the difference, this SensorControl we must be familiar with its principles and development. We will explain it in the SensorController chapter. Storage System We must have the following understanding of the storage system: Based on the design of multiple CPUs, each CPU has its own independent and shared storage system.

TI reserves 128ROM as factory firmware to implement some DriverLib, TI-RTOS, and BLE-Stack functions;

TI reserves 8KB of Cache as pre-fetch cache, which can be configured through RAM, that is, the RAM available to our users can be configured from 20KB to 28KB.

Note: The above memory space mapping diagram does not include complete functional registers and peripherals. For the complete memory mapping diagram, click C:/ti/simplelink_cc2640r2_sdk_1_35_00_33/docs/driverlib_cc13xx_cc26xx/cc26x0r2/register_descriptions/CPU_MMAP/CPU_MMAP.html

Being familiar with the above memory space mapping diagram and the starting address of each memory is very important for us to control the code project in the future.

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