Download>Category>FPGA/CPLD>Xilinx>vim plugin: a tool to improve Verilog and UVM testbench coding efficiency

rar

vim plugin: a tool to improve Verilog and UVM testbench coding efficiency

2013-07-01
121.34KB
Points it Requires : 1

repReport

Document Introduction
You Might Like
Recommended Downloads

Verilog part: Automatically generate port signal list; Automatically generate signal declaration; Automatic instantiation (can recognize changes in connections after instantiation, better than emacs); Automatically generate some regular codes (similar to generate statements); User-defined parameterized templates; UVM part: Automatically generate interface; Automatically generate uvm_field_*; Templates for various uvm classes; Verilog & UVM Aide.pdf Installation: plugin.rar Copy vlog_utilities.vim and uvm_utilities.vim to ~/.vim/plugin; vlog_aide.tar Copy vlog_aide to any directory, assuming ~/xxx/; Assume that the path of your rlt file is: /proj/aaa/rtl; Add the following code to your .cshrc; setenv VLOG_AIDE_HOME ~/xxx setenv VLOG_LIBRARY_PATH ~/xxx/lib setenv VLOG_AIDE_RTL_PATH /proj/aaa/rtlExample is under vlog_aide/example

unfold

You Might Like

Uploader

: 论文帝

Recommended ContentMore

Open source project More

Popular Components

Searched by Users

Just Take a LookMore

The old version of the forum homepage has a bug
RT, all garbled
During this extraordinary period, go out less and study more: Many TI practical courses are presented. If your body cannot be on the road, let your soul be on the road.
The list of winners is as follows. Congratulations to everyone.username prizeHawthorn pot cake Mijia desk lampMersenne Mijia desk lampisunspot@ Mijia desk lamperic.xu Mijia desk lampLi Jibin Mijia des
Free Document Download | Littelfuse Power Control and Circuit Protection Solutions
The following are Littelfuse's experiences and solutions in the fields of [automation and industrial power supply], [new energy vehicles and charging piles], [communications and data center management
There are residual line segments in pads that cannot be selected. What is the reason?
There are residual line segments in pads that cannot be selected. What is the reason?
LED constant current control circuit
For a typical constant current control circuit like the one above, is there a requirement for the minimum voltage between the MOS tube DS? For example, if I want to drive an LED, the voltage between t
January 21 Live Broadcast Review: ADI's Vital Signs Monitoring Solutions in Wearable Products
2020Show me what I think of XXX
Experts from Station B come to help: Portable, fast-charging, and temperature-adjustable soldering iron, let’s get started?
Advanced Hydraulic PDA Stand (Non-Swivel)
What is the salary of embedded engineers in 2022?

Trending Downloads

Trending ArticlesMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews

Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号京ICP备10001474号-1 电信业务审批[2006]字第258号函

京公网安备 11010802033920号

×