Ten major misunderstandings in PCB design - the endless equal length (Part 2)[Copy link]
Author: Wu Jun
Part 1
About Equal Length and Equal Timing
After publishing the first article in the winding series, I started preparing for the US seminar, and then went on a month-long business trip. Finally I have time to continue this topic. As mentioned before, it is now popular to say important things three times: Equal length has never been the goal, the system requires equal timing... Except for the equal timing within the differential pair for phase, most of the equal timing is for timing! To wind wires for timing, you must understand the timing relationship and the timing diagram. Every time you see a timing diagram, your eyes go dark, right? Timing is a very headache and complicated topic for everyone, so Mr. Gaosuo Xiaochen tried to use the relationship between two couples to explain the timing problem in the previous timing topic. I wonder how many people really understood the tongue twister metaphor? It seems that people born in the 80s and 90s quickly understood Xiaochen's meaning, while people born in the 70s generally said that they were more confused. It is a huge challenge to explain the timing problem simply. Mr. Gaosuo's spirit is to face the challenge head-on and continue to fight. My goal is not to show you complicated timing diagrams, nor to use any metaphors and associations, so that everyone can understand timing simply.
Borrow a good picture to understand the three main timing systems at a glance (here ignore the less used internal synchronous clock system) Parallel bus includes the early common clock and the popular source synchronous clock, and then there is the serial bus. It is also very simple to distinguish the three systems. The subsequent articles will explain them one by one.
Part 2
Common clock timing
The common clock parallel bus, a technology more than ten years ago, cannot keep up with the needs of high-speed design, but there are still some applications now, such as the common Local bus is basically a common clock bus. There are also CPCI bus, PCIX bus, early SDRAM, etc. The main feature of judging whether it is a common clock bus is that the external clock distributor (or FPGA) sends the clock line to the sending and receiving chips respectively. As shown in the figure below, if the external synchronous clock can be found, it must be a common clock bus.
The timing characteristic of the common clock bus is that at the previous edge of the clock, the sending chip sends out the data, and then at the next clock edge, the receiving chip receives the data. In order to simplify the understanding later, it is assumed that the time when the clock reaches the driver and the receiver is the same, that is, the clock lines are of equal length (this is also the most common design idea). The factors that affect timing include Tco, Tskew, Tjitter, Tcrosstalk... It seems complicated. In simple terms, as long as two conditions are met, the timing requirements can be achieved: Within one clock cycle, the data must be sent from the driver end to the receiving end, and there must be enough setup time. Before the second data arrives, the previous data must have enough hold time. To meet condition 1, Tclk is required to accommodate all the time required for the data to arrive, including data output delay (Tco), data flight time (Tflighttime), data hold time requirement (Tsu), and all the factors that affect timing (Tcrosstalk, Tjitter...), and all these factors must take the worst case.
TPCB skew+Tclock skew +Tjitter +Tco data +Tflt data +Tsetup" [size="4]" align]="" b][="" data="" min）之后达到，数据必须在下个数据达到之前有足够的保持时间。[="" min）加上最小数据飞行时间（tflighttime="" size]="" size][="" skew="" skew+tpcb="">Thold
When actually designing, we need to find the corresponding data in the device manual to perform timing calculations. From an understanding perspective, it is not that complicated.
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