PIC32 code is programmed successfully but does not run

asdmaill

PIC32 code is programmed successfully but does not run [Copy link]

 

As the title says, the compiler prompts that the programming is successful, but the program does not run, the MCLR pin is always low, all IO ports are high, and the chip is always in reset state. Is there something wrong?

mzb2012

Well, first you have to rule out whether it is a hardware problem or a problem with your program configuration.

asdmaill

As for the hardware, it can be programmed correctly, so there should be no problem. During the programming process, I measured the MCLR pin with a voltmeter, and it was correct when it was at a high level. It is probably a configuration problem, but I don't know where the configuration problem is. I didn't go to bed until after 2 o'clock last night.

tiankai001

Check the clock configuration.

asdmaill

Internal FRC used

ddllxxrr

Check whether there is a reset and the configuration of the crystal oscillator. It should be a configuration problem.

asdmaill

The key is why the MCLR pin is always low. Even if it is not configured correctly, the reset is controlled by hardware.

asdmaill

#pragma config FMIIEN = ON // Ethernet RMII/MII Enable (MII Enabled) #pragma config FETHIO = ON // Ethernet I/O Pin Select (Default Ethernet I/O) #pragma config PGL1WAY = ON // Permission Group Lock One Way Configuration (Allow only one reconfiguration) #pragma config PMDL1WAY = ON // Peripheral Module Disable Configuration (Allow only one reconfiguration) #pragma config IOL1WAY = ON // Peripheral Pin Select Configuration (Allow only one reconfiguration) #pragma config FUSBIDIO = ON // USB USBID Selection (Controlled by the USB Module) // DEVCFG2 #pragma config FPLLIDIV = DIV_8 // System PLL Input Divider (8x Divider) #pragma config FPLLRNG = RANGE_34_68_MHZ// System PLL Input Range (34-68 MHz Input) #pragma config FPLLICLK = PLL_FRC // System PLL Input Clock Selection (FRC is input to the System PLL) #pragma config FPLLMULT = MUL_128 // System PLL Multiplier (PLL Multiply by 128) #pragma config FPLLODIV = DIV_32 // System PLL Output Clock Divider (32x Divider) #pragma config UPLLFSEL = FREQ_24MHZ // USB PLL Input Frequency Selection (USB PLL input is 24 MHz) // DEVCFG1 #pragma config FNOSC = FRCDIV // Oscillator Selection Bits (Fast RC Osc w/Div-by-N (FRCDIV)) #pragma config DMTINTV = WIN_127_128 // DMT Count Window Interval (Window/Interval value is 127/128 counter value) #pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Enable SOSC) #pragma config IESO = ON // Internal/External Switch Over (Enabled) #pragma config POSCMOD = OFF // Primary Oscillator Configuration (Primary osc disabled) #pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled) #pragma config FCKSM = 0//CSECME // Clock Switching and Monitor Selection (Clock Switch Enabled, FSCM Enabled) #pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576) #pragma config WDTSPGM = STOP // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming) #pragma config WINDIS = NORMAL // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode) #pragma config FWDTEN = 0//OFF // Watchdog Timer Enable (WDT Disabled) #pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window size is 25%) #pragma config DMTCNT = DMT31 // Deadman Timer Count Selection (2^31 (2147483648)) #pragma config FDMTEN = 0//OFF // Deadman Timer Enable (Deadman Timer is enabled) // DEVCFG0 #pragma config DEBUG = OFF // Background Debugger Enable (Debugger is enabled) #pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled) #pragma config ICESEL = ICS_PGx1 // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1) #pragma config TRCEN = OFF // Trace Enable (Trace features in the CPU are enabled ) #pragma config BOOTISA = 0//MIPS32 // Boot ISA Selection (Boot code and Exception code is MIPS32) #pragma config FECCCON = OFF_UNLOCKED // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable)) #pragma config FSLEEP = OFF // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode) #pragma config DBGPER = PG_ALL // Debug Mode CPU Access Permission (Allow CPU access to all permission regions) #pragma config SMCLR = 0//MCLR_POR // Soft Master Clear Enable bit (MCLR pin generates a normal system Reset) #pragma config SOSCGAIN = GAIN_2X // Secondary Oscillator Gain Control bits (2x gain setting) #pragma config SOSCBOOST = ON // Secondary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator) #pragma config POSCGAIN = GAIN_2X // Primary Oscillator Gain Control bits (2x gain setting) #pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator) #pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality ) // DEVCP0 #pragma config CP = OFF // Code Protect (Protection Disabled) #includeoscillator) #pragma config POSCGAIN = GAIN_2X // Primary Oscillator Gain Control bits (2x gain setting) #pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator) #pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality) // DEVCP0 #pragma config CP = OFF // Code Protect (Protection Disabled) #includeoscillator) #pragma config POSCGAIN = GAIN_2X // Primary Oscillator Gain Control bits (2x gain setting) #pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator) #pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality) // DEVCP0 #pragma config CP = OFF // Code Protect (Protection Disabled) #include
The above is the configuration code, using the internal FRC

asdmaill

Watchdog and program monitoring timers are turned off

asdmaill

asdmaill

The above is my download and reset circuit. I have used this circuit before with DSPIC and it worked fine.

dl265361

Check the hardware

asdmaill

After checking and re-soldering the chip, the problem remains

asdmaill

I checked the power supply ripple with an oscilloscope and it was normal.

ienglgge

asdmaill posted on 2018-2-5 16:32 I used an oscilloscope to check the power supply ripple and other things, and they are all normal

Reset, crystal oscillator, power supply, check the welding. Measure the waveform. Try another normal program.

asdmaill

I made the board myself. Now the test code is just written and I am ready to test the board.

asdmaill

Why is the MCLR pin always at a low level? When the code is burned, it is correct and can be pulled to 3.3V. After burning, MCLR is always at a low level.

asdmaill

I disconnected the power supply, and IPE prompted the target to be removed. When I connected the power supply, IPE prompted the target to be found, and then displayed the device ID version number A1

asdmaill

Therefore, I think there is no problem with the hardware, but a configuration problem. It should be that the configuration registers of DEVCFG are not configured correctly, but I don't know which bit is not configured correctly

电子微创意

The configuration bits only configure the clock and ICSP pins, and the others should remain at default. If it is really necessary, it is recommended to remove SW1 and C2 and directly pull MCLR high with a resistor.