How to use CoolMOS in a continuous conduction mode totem pole power factor correction circuit

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How to use CoolMOS in a continuous conduction mode totem pole power factor correction circuit [Copy link]

Author: Lin Xianchong and Hong Shiheng, Application Engineers, Infineon Technologies

1 Introduction

Power factor correction is to shape the input current of the power supply into a sine wave and synchronize it with the power supply voltage to maximize the actual power drawn from the power supply. In a perfect PFC circuit, the input voltage and current are in a pure resistance relationship, without any input current harmonics. At present, the boost topology is the most common topology for PFC. In terms of efficiency and power density, it is necessary to move towards a bridgeless type in order to further reduce the use of devices, the number of power devices and the loss in the conduction path. Among them, the totem-pole power factor correction circuit (totem-pole PFC) has proven to be a successful topology, and its control method has also matured.

Generally speaking, the performance of super junction MOSFET in totem pole applications, especially in continuous conduction mode, will be greatly reduced. The reason is the hard-cut loss and reverse recovery loss of the parasitic diode generated in the high-frequency bridge arm that controls the energy during the switching process. To overcome this application problem, the countermeasures currently used in the market are mostly to use wide bandgap semiconductors.

In order to use common switching devices in totem pole PFC, this article introduces the solution of pre-charging circuit. Compared with the use of wide bandgap semiconductors, the power semiconductor devices of this solution are more common and easier to obtain, and are provided to users as a design reference.

2. Basic working principle

Before introducing the new method, we first introduce the instantaneous characteristics of super junction semiconductor switching. Because the semiconductor design trend is still to reduce switching losses to increase product power density, that is, to reduce the loss of VI crossover during the switching process, the common practice of semiconductor manufacturers is to design the switch equivalent output capacitance (Coss) characteristics as a nonlinear curve: at low voltage, the Coss value is large, and as the voltage increases, the capacitance value drops sharply when approaching medium voltage, as shown in the Coss characteristic curve on the left of the figure below (this article uses Infineon CoolMOS as an example), which can reduce the loss area of VI crossover. With the evolution of process technology, the Coss change curve changes more sharply, which can be clearly compared between the new and old generations of MOSFET. The following figure on the right compares the difference in Coss characteristics and switching losses between the new and old generations of MOSFET.

Figure 1: Coss curve and switching loss comparison

For half-bridge applications, the output capacitance characteristics of two MOSFETs with the same characteristics after bridging are shown in Figure 2. In half-bridge applications, zero voltage switching is generally valued, because the energy storage loss (Qoss) and reverse recovery characteristics (Qrr) of the total output capacitance of the MOSFET will greatly increase the loss of the half-bridge architecture during hard switching. In the half-bridge, the maximum value of the equivalent output capacitance as shown in the figure occurs when either arm switch is 0V. As the voltage of either arm increases to about 20~30V, the equivalent output capacitance decreases sharply. This characteristic will be used in the compensation circuit to be introduced next.

Figure 2: Half-bridge CoolMOS Coss voltage variation curve

Figure 3 below is an example of a pre-charge circuit. In this topology, hard commutation of the diode mode switch occurs in each switching cycle. In some half-bridge structures, considering the energy accumulated in the inductor, Q2 usually operates in a soft switching state after Q1 is turned off. However, when Q2 is turned off, due to the continuous nature of the inductor current, this current flows through its body diode. When Q1 is turned on, hard commutation of the Q2 body diode current occurs.

Figure 3: Schematic diagram of high-frequency half-bridge pre-charging action for totem pole architecture

By adding a pre-charge circuit, the MOSFET working in diode mode can be pre-charged to a specific voltage, such as 24V, before the channel is turned on. This can greatly reduce the losses related to Qoss and Qrr. Therefore, the overall performance of CoolMOS in CCM Totem Pole PFC can be greatly improved.

The proposed pre-charging solution requires additional devices for each power switch in the half-bridge: a high-voltage Schottky diode (D1 and D2 in the figure) and a low-voltage MOSFET (Q3 and Q4 in the figure). Two voltage sources are also required to drive the half-bridge and low-voltage MOSFET (13V) and the MOSFET drain-source voltage (24V). In addition, the Rx-Cx and Ry-Cy filters included at the driver input set the correct timing for the PWM signal without the need for additional control signals.

Figure 4: Totem pole architecture pre-charge circuit timing control diagram

The main waveforms are shown in Figure 4. In the state before t0, the inductor is charged through Q1. Once Q1 is turned off, the inductor current flows through Q2, first through its body diode, and then through the device channel after Q2 is turned on. Therefore, in the Totem pole PFC, Q2 works in zero voltage (ZVS) switching when it is turned on. At t0, the PWM A signal is set low, and after a certain delay time (the delay of Ry and Cy), the gate-source voltage signal (VGS) of Q2 is also set low at t1. During the dead time of the half bridge (t1 to t2), the inductor current is freewheeling through the body diode of Q2. Before t2, the VDS of Q2 is clamped to ground and all bootstrap capacitors (except CHS_P) are charged by the drive voltage and 24V voltage (Figure 5a and b). Then after the dead time, PWM B is set high, generating a short gate voltage of Q4 through Cx and Rx. Therefore, the pre-charged Q4 will be turned on at t2 (Figure 5c), and the pre-charge current flows through the network from Q4 to D2 to Q2. The amplitude of this pre-charge current must be higher than the freewheeling current flowing through the body diode of Q2. At the end of the pre-charge current (t3), the drain-source voltage of Q2 is pre-charged to 24V.

As shown in Figure 4, the pre-charge current waveform has two peak pulses: the first one between t2 and t3 is related to the Coss of Q2. The second one between t3 and t4 is smaller in amplitude and is formed by the resonance of the stray inductance of the pre-charge loop. Q1 is delayed until t4 to turn on, at which time the Coss of Q2 has been exhausted by 24V. As shown in Figure 5d, when Q1 is turned on, the bootstrap capacitor for Q3 is charged from the bootstrap capacitor of Q1. As can be seen from Figure 4, when Q1 or Q2 is turned on, the pre-charged Q4 or Q3 has not been turned off, so as to ensure low loss at the moment of Q1 or Q2 turning on. If this pulse is too short, there is a high probability that Q2 will undergo hard commutation at the moment of turning on. If it occurs during multiple consecutive events, it will have destructive results.

When the PWM B signal is set low, similar to before, Q1 will be delayed until t5 to turn off (delay of Ry and Cy). After the channel is turned off, the Coss of Q1 will be charged to 400V and the Coss of Q2 will be discharged to 0V, resulting in zero voltage switching (ZVS) of Q2. This is the case for switch-to-diode switching in PFC applications. In this case, the pre-charging circuit of the high-side switch (CHS_DP to Q3 to D1) will not have any impact on the operation of the MOSFET-based half-bridge circuit.

When the load or inductor current is high enough, Coss will be fully charged and discharged, thereby achieving the purpose of zero voltage switching (ZVS). However, if the inductor current is not enough to charge and discharge the Coss equivalent to the half-bridge, hard switching will occur. Refer to the dotted line after t5 in Figure 4. In this case, the pulse voltage applied to Q3 charges the Coss of Q1 to 24V through D1. Once Q2 is turned on, its drain-source voltage will drop to close to zero again, achieving a relatively smooth switch to the parasitic diode.

Figure 5: Schematic diagram of hard commutation transient operation of pre-charging circuit with pre-charging circuit added

3. Test results

This section shows the specifications and performance of the 3300W bridgeless CCM Totem pole PFC evaluation board. This evaluation board implements the pre-charge circuit introduced in this article and uses 600 V CoolMOS CFD7 to implement CCM Totem pole PFC. Its parasitic diode characteristics are low reverse recovery charge and are not easily damaged by hard switching under extreme conditions. Figure 6 shows the complete circuit diagram. The high-frequency part uses CoolMOS IPT60R090CFD7 in parallel and the pre-charge circuit uses BSZ440N10S3.

Figure 7 shows the performance and specifications of the evaluation board under steady-state and dynamic conditions. The converter operates at 65kHz switching frequency and is suitable for high-voltage single-voltage input only. The minimum AC input voltage is 176Vac rms.

Figure 6: Evaluation board circuit diagram

Figure 7: Performance Specifications

The figure below shows the actual test results of steady-state efficiency, showing the efficiency measurement values at different AC voltages. This measurement result includes the basic loss of the controller and fan (6W aux power).

Figure 8: Steady-state efficiency test results

The figure below shows the main working waveforms of the Totem Pole PFC, which also includes the waveform of the pre-charge circuit. It can be seen from the waveform that the pre-charge current only appears in the corresponding AC cycle and has no effect on the opposite AC cycle.

Figure 9: Steady-state input voltage, inductor current and pre-charge current waveforms

Figures 10 and 11 show the drain-source voltage waveforms for 0A and 23A inductor currents (under full-load steady-state operation), respectively, including the necessary pre-charge current waveforms. The measured waveforms are consistent with the voltage and current pre-charge waveforms shown in the previous section (Figure 4).

Figure 10: No-load pre-charge current instantaneous waveform

Figure 11: Pre-charge current instantaneous waveform at full load

4 Conclusion

This article introduces a solution for bridgeless continuous conduction mode totem pole PFC using MOSFETs, which achieves 99% peak efficiency at a 1U form factor and 80W/inch3 power density. This evaluation board uses Infineon's 600V CoolMOS CFD7 series MOSFETs and a pre-charge circuit. The pre-charge circuit reduces the losses of Qoss and Qrr by providing charge from a low-voltage voltage source. The working principle of pre-charge has been introduced in the previous article for readers to know. The combination of CoolMOS CFD7 and the pre-charge circuit, as well as the CoolMOS S7 selected for the low-frequency bridge arm, demonstrates high performance efficiency levels with a cost-effective circuit. In addition, although the pre-charge circuit increases the number of semiconductor devices, the auxiliary circuits can all use surface mount packages, so a high power density power supply design can be achieved.

5. References

1. Evaluation board EVAL_3K3W_TP_PFC_SIC

2. Design guide MOSFET CoolMOS C7 600V