How does the SPI bus work?

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How does the SPI bus work? [Copy link]

SPI is a high-speed, full-duplex, synchronous communication bus, and it only occupies four lines on the chip pins, saving the chip pins, and saving space for PCB layout, providing convenience. It is precisely because of this simple and easy-to-use feature that more and more chips now integrate this communication protocol. SPI is a ring bus structure, consisting of ss (cs), sck, sdi, and sdo. Its timing is actually very simple. It is mainly under the control of sck that two bidirectional shift registers exchange data. The
　　SPI bus is a three-wire synchronous interface launched by Motorola. It communicates in a synchronous serial 3-wire mode: a clock line SCK, a data input line MOSI, and a data output line MISO; it is used for full-duplex, synchronous serial communication between the CPU and various peripheral devices. The main features of SPI are: it can send and receive serial data at the same time; it can work as a host or a slave; it provides a frequency-programmable clock; it sends an end interrupt flag; write conflict protection; bus competition protection, etc.
　　The SPI bus has four working modes (SP0, SP1, SP2, SP3), among which the most widely used are SPI0 and SPI3. In order to exchange data with peripherals, the SPI module can configure the output serial synchronous clock polarity and phase according to the peripheral working requirements. The clock polarity (CPOL) has no significant impact on the transmission protocol. If CPOL=0, the idle state of the serial synchronous clock is low; if CPOL=1, the idle state of the serial synchronous clock is high. The clock phase (CPHA) can be configured to select one of two different transmission protocols for data transmission. If CPHA=0, the data is sampled at the first transition edge (rising or falling) of the serial synchronous clock; if CPHA=1, the data is sampled at the second transition edge (rising or falling) of the serial synchronous clock. The
　　clock phase and polarity of the SPI master module and the peripheral communicating with it should be consistent.
　　SPI timing details---The moment when the SPI interface outputs the first bit of data in mode 0 The SPI interface has four different data transmission timings, depending on the combination of the two bits CPOL and CPHL. Figure 1 shows these four timings, and the relationship between the timing and CPOL and CPHL can also be seen from the figure.
　

　　Figure 1
　　CPOL is used to determine the idle level of the SCK clock signal. When CPOL=0, the idle level is low. When CPOL=1, the idle level is high. CPHA is used to determine the sampling time. When CPHA=0, the first clock edge of each cycle is sampled. When CPHA=1, the second clock edge of each cycle is sampled. Since the device I use works in the timing of mode 0 (CPOL=0, CPHA=0), Figure 1 is simplified to Figure 2, and only the timing of mode 0 is concerned.
　

　　In Figure 2
　　, we focus on the first clock cycle of SCK. Data is sampled at the leading edge of the clock (rising edge, the first clock edge), and data is output at the trailing edge of the clock (falling edge, the second clock edge). First, let's look at the master device. The data bit1 output by the output port (MOSI) of the master device is sampled by the slave device at the leading edge of the clock. So when does the master device output bit1? The output time of bit1 is actually before the SCK signal is valid, half a clock cycle earlier than the rising edge of SCK. The output time of bit1 has nothing to do with the SSEL signal. Let's look at the slave device again. The input port MISO of the master device also samples the bit1 output by the slave device at the leading edge of the clock. So when does the slave device output bit1? The slave device outputs bit1 immediately after the SSEL signal is valid, even though the SCK signal has not yet taken effect.
　

　　From this picture, we can clearly see how bit1 of the master and slave devices is output.