Good design methods and misunderstandings in FPGA design
Total of 3 lessons1 hours and 2 minutes and 52 seconds
Huaqing Vision Training Tutorial, Real-time Linux Technology: How to apply real-time features in embedded LINUX Embedded Linux Optimization: Accelerate the process of system startup and application startup Embedded system boot program transplantation of FPGA DSP application C6000 DSP software development environment CCS Introduction to FPGA Typical application areas and solutions
Total of 6 lessons5 hours and 48 minutes and 18 seconds
Red Hurricane FPGA Popularization Action
Total of 6 lessons4 hours and 21 minutes and 5 seconds
This tutorial mainly teaches the grammatical rules of VHDL language and some examples in 36 lessons. It mainly focuses on software applications and only briefly describes the structure of actual hardware integrated circuits.
Total of 36 lessons1 days and 3 hours and 47 minutes and 30 seconds
Ray tracing demonstration using OpenCL on SoC
Total of 1 lessons3 minutes and 58 seconds
Altera Cyclone V SoC video application playback demonstration
Total of 1 lessons1 minutes and 58 seconds
The industry's most flexible ARM® Cortex™-M0 low-cost PSoC development platform.
Total of 1 lessons1 minutes and 46 seconds
Altera2012 Asia Innovation Design Competition CN099 Video Introduction-01
Total of 1 lessons2 minutes and 14 seconds
Introduction to Xilinx training resources
Total of 1 lessons4 minutes and 19 seconds
ZING SoM—the industry’s smallest Zynq system module
Total of 1 lessons2 minutes and 31 seconds
Smarter Solution for OTN
Total of 1 lessons9 minutes and 4 seconds
RX Jitter Margin Analysis Demonstration for Xilinx 7 Series Serial Transceivers
Total of 1 lessons3 minutes and 46 seconds
Smarter Solution for packet processing
Total of 1 lessons5 minutes and 27 seconds
Smarter Solution applied to data center (DataCenter)
Total of 1 lessons6 minutes and 36 seconds
Flexible Mixed Signal Processing Technology Demonstration
Total of 1 lessons3 minutes and 59 seconds
Run SoftPLC solution on Zynq platform
Total of 1 lessons2 minutes and 37 seconds
Virtex-7 X690T GTH Demo
Total of 1 lessons3 minutes and 48 seconds
Virtex-5 Power Consumption Estimation and Measurement Demonstration
Total of 1 lessons33 minutes and 7 seconds
![[Chinese explanation] Vivado UltraFast design method](http://11.eewimg.cn/training/files/course/2018/04-01/224151f37be5443993.png?50)
[Chinese explanation] Vivado UltraFast design method
Total of 1 lessons51 minutes and 15 seconds
Altera's next-generation 20-nm family of products introduces a number of industry firsts, including a single-chip 28-Gbps backplane-enabled transceiver, a 40-Gbps chip-to-chip transceiver, and CEI-56G compatible 56-Gbps transceiver The development route of the device has enabled chip-to-chip and chip-to-module applications. These latest innovations triple the switching bandwidth and front-panel port density for fixed-line, military and broadcast applications compared to Altera's current backplane-enabled transceivers, enabling eight lanes of 400-Gbps optical module communications.
Total of 1 lessons1 minutes and 19 seconds
Can your design quickly adapt to changing Ethernet protocols? Can you meet increasing performance requirements? Watch this video to learn how Industrial Networking Suite and flexible, low-power FPGAs can help you solve these challenges in embedded industrial applications.
Total of 1 lessons10 minutes and 4 seconds
Are you going to hit some notes? With our MAX® V CPLD Development Kit, you can hit some notes while evaluating your board's ability to drive analog chips. The kit also provides you with a platform for prototyping CPLD applications using MAX V CPLDs. You'll find that if value is the key consideration when selecting a CPLD, MAX V devices are your best choice because of their low power consumption, low cost, and reliable functionality.
Total of 1 lessons7 minutes and 23 seconds
Timing and signaling are critical factors in external memory design. Altera's new memory controller and UniPHY further improve systems by enabling higher clock data rates, reduced latency, ease of use, ease of debugging, voltage and temperature (VT) tracking, and PLL/DLL sharing. performance. In the demonstration, you will learn about the design flow, how to initialize the memory controller, and design and debug it.
Total of 3 lessons44 minutes and 25 seconds
In order to give full play to the technical advantages of WDR sensors, it is necessary to adopt a new generation of ISP technology to process full-range real-time scenes at high pixel rates based on advanced algorithms.
Total of 2 lessons27 minutes and 18 seconds
Timing analysis is a critical factor in 65 nm and smaller process geometries. You should know how to easily set timing constraints, generate timing reports that improve timing analysis performance, and how to improve FPGA timing performance. In this technical seminar, you will learn how to solve these challenges by understanding the basics of timing analysis and SDC-based timing analysis methods. You'll also learn about other timing analysis resources.
Total of 1 lessons21 minutes and 19 seconds
Challenges faced by video and image processing designers (VIPs) include how to improve image format conversion quality, offload DSP loads, reduce system costs, and bring products to market in a timely manner. Altera Video Imaging Workbench is the ideal solution to quickly solve these challenges. In this technical VIP seminar, you will learn about Altera's VIP workbench and VIP design methods through live demonstrations.
Total of 1 lessons15 minutes and 46 seconds
Using a simple design flow, you can easily develop PCIe designs with Altera embedded hard IP. This session introduces the key features of PCIe hard IP embedded in Stratix, Arria, and Cyclone family FPGAs.
Total of 2 lessons23 minutes and 1 seconds
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