This set of courses is a recorded course of Xiaomei’s field training class in 2019. It is rich in content, high in knowledge, and carefully edited, so the viewing experience is good. The course arrangement is divided into a foundation solidification stage, a system modeling stage, and an example strengthening stage.
Total of 70 lessons1 days and 11 hours and 37 minutes and 41 seconds
This lecture will introduce how to use Intel's tools to implement deep learning derivation and task acceleration on FPGA. We will also discuss deep learning task derivation and toolkits - providing a unified interface when deploying derivation tasks for different Intel product architectures, different frameworks, and different network architectures. And how the deep learning architecture FPGA kit combines the function calls of the deployment toolkit with the FPGA device.
Total of 1 lessons25 minutes and 25 seconds
The video explains the use of NIOS ii through practical projects of hello world, PIO, UART, and SDRAM.
Total of 7 lessons3 hours and 51 minutes and 54 seconds
Based on Verilog, we explain FPGA in detail from hardware, software and actual combat. Each chapter of the actual combat chapter includes five parts: knowledge introduction, experimental tasks, hardware design, program design, and download verification. Step by step teaching, come and learn about FPGA with Brother Atom
Total of 83 lessons1 days and 18 hours and 53 minutes and 50 seconds
This series of teaching videos will lead you from scratch to master HLS and UltraFAST design methods from scratch, step by step, to help you become a master of system design and algorithm acceleration! This course includes five topics: the design process of Vivado HLS, coding style when describing algorithms in C or C++, optimization methods of for loops, optimization methods of arrays, and implementation of input/output ports.
Total of 23 lessons4 hours and 38 minutes and 6 seconds
H.265 Video Encoder IP Core is an open source H.265 hardware video encoder that implements most of the functions of H.265 (or HEVC). It was developed by the research team of Professor Fan Yibo of the Video Image Processing Laboratory (VIP Lab) of the State Key Lab of ASIC & System, Fudan University, and is open source. Any organization or individual can use the above code for research and production purposes free of charge, and VIP Lab will continue to update and maintain the development of the H.265 hardware video encoder.
Total of 8 lessons2 hours and 4 minutes and 36 seconds
FPGA Simple Design Principles and Applications-Chapter 1
Total of 3 lessons1 hours and 59 minutes and 18 seconds
"Verilog HDL Design and Practice" is divided into four parts: basic operations of the ModelSim simulation tool and QuartusⅡ development tool, Verilog HDL syntax introduction, FPGA example design and NiosⅡ example design based on Qsys. First, the basic operations of QuartusII are introduced, including project creation, code editing, schematic design, VerilogHDL code design, waveform simulation based on QuartusII and ModelSim, and downloading of FPGA configuration files and other basic operations related to FPGA design. Then, the basic syntax of VerilogHDL is introduced one by one in the form of VerilogHDL knowledge points with VerilogHDL program examples. Then, using examples as the starting point, from simple to complex, the modeling of combinational circuits, sequential circuit modeling and the design of comprehensive examples are introduced.
Total of 26 lessons8 hours and 2 seconds
Explain the steps to install vivado and JTAG driver under ubuntu
Total of 2 lessons21 minutes and 1 seconds
This tutorial explains the basics of FPGA, introduction to SOC, DMA and VDMA, Linux, HLS images and PCIE. It is suitable for the following applications: high-speed communication; machine vision, robots; servo systems, motion control; video acquisition, video output, consumer electronics; early stage of project research and development Verification; learning for developers in electronic information engineering, automation, communication engineering and other electronic related majors
Total of 58 lessons1 days and 9 hours and 42 minutes and 59 seconds
The goal of the course is to enable students to master the means, methods and ideas of hardware description language design of digital systems through the study of this course and other related courses, master commonly used EDA development software, and integrate HDL hardware description language programming methods and FPGA development technology and conform to Engineering specifications and system design techniques are organically integrated. At the same time, we can understand the latest developments in the subject, connect theory with practice, and cultivate students' practical ability and comprehensive innovation ability.
Total of 30 lessons20 hours and 45 seconds
Basic operations of QuartusⅡ software, introduction to VHDL syntax, FPGA design examples and NiosⅡ design examples. First, the basic operations of Quartus II are introduced, including FPGA design such as project creation, code editing, schematic design, VHDL code design, simulation, and downloading of FPGA configuration files. Afterwards, the basic syntax of VHDL is introduced in detail, and VHDL knowledge points are introduced one by one with VHDL program examples, so that readers can be freed from the complex VHDL syntax. Then, using examples as the starting point, from simple to complex, the modeling of combinational circuits, sequential circuit modeling, and the design of comprehensive examples are introduced. Next, in the explanation of Nios II, the temperature sensing system based on DS18820 and the clock real-time display system based on PCF8563.
Total of 22 lessons8 hours and 30 seconds
Total of 2 lessons2 hours and 12 minutes and 48 seconds
Total of 1 lessons56 minutes and 55 seconds
Total of 4 lessons6 hours and 48 minutes and 28 seconds
Total of 5 lessons55 minutes and 35 seconds
Total of 6 lessons1 hours and 31 minutes and 7 seconds
Using multiple templates helps us save time. Ming Deyang's template includes counters, state machines, FIFOs and module structures of the minimalist design method, which are the most common parts of RTL code. When using these templates, engineers only need to fill in the blanks in order to quickly design, saving a lot of time.
Total of 2 lessons34 minutes and 48 seconds
Total of 7 lessons1 hours and 33 seconds
Total of 7 lessons1 hours and 38 minutes and 11 seconds
Total of 5 lessons1 hours and 31 minutes and 51 seconds
Total of 36 lessons23 hours and 34 minutes and 19 seconds
Total of 29 lessons1 days and 2 hours and 19 minutes and 34 seconds
An in-depth look at SoC FPGA performance and how to leverage it, with an emphasis on software development tools and multi-core debugging.
Total of 14 lessons41 minutes and 43 seconds
Based on the ZX_2FPGA development board, we teach you step by step how to install the design tool (Altera Quartus II) and write programs in Verilog to conduct simple experiments.
Total of 5 lessons3 hours and 47 minutes and 36 seconds
Light flow and pedestrian detection via OpenCL
Total of 1 lessons2 minutes and 49 seconds
Design input using hard-core floating point
Total of 1 lessons3 minutes and 23 seconds
About the speaker: Wang Minzhi, who has worked in many scientific research institutes and has been engaged in research and development work in radar, communications and medical electronics. Participated in the research and development of many types of shipborne radars, mainly responsible for the development of digital circuits. The current research directions are digital medical development, digital signal processing part of PET and TDC implementation based on FPGA. His work "In-depth Understanding of Altera FPGA Application Design" is highly praised by engineers and has a good reputation.
Total of 3 lessons1 hours and 16 minutes and 0 seconds
Application of FPGA in the field of video processing
Total of 2 lessons32 minutes and 47 seconds
FPGA software and hardware co-design
Total of 35 lessons1 days and 3 hours and 17 minutes and 36 seconds
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