Adaptive equalizer system electronic circuit

Adaptive cable equalizers are an essential component of the receiver front end for serial digital video (SDV) broadcast and serial telecommunication equipment, and they can also be used in other types of wired communication systems. The equalizer interfaces directly with the transmission line, restoring the signal amplitude and bandwidth losses caused by the cable. Because the equalizer is directly connected to the cable, it is very susceptible to ESD, EMI/RFI, and device-generated noise, and the operating characteristics of the equalizer tend to increase the effects of noise in the design. A robust system using an interference-resistant adaptive cable equalizer must also maintain the good operating characteristics of the equalizer, such as wide input dynamic range, wide signal bandwidth, low residual output noise, high input return loss, and maximum equalized cable length.

ESD, EMI/RFI and device noise are the three main interference modes in wired communication systems: ESD can damage or destroy active and passive devices inside and outside the circuit; EMI/RFI can affect the system's signal processing, and in severe cases can cause the failure of the system's basic functions; the noise generated by the device can affect the operation of the circuit, reduce its performance, and may also cause system failure.

Technical Challenges of Adaptive Equalizer Design

Designing a robust system that can handle the above interference is a challenge. Adaptive cable equalizers are not simple digital devices, which is a basic fact that designers must carefully consider. National Semiconductor's CLC014, CLC012 and the latest CLC034 adaptive equalizers are high-performance analog devices. They are high-gain, high-bandwidth, analog, RF, AGC amplifier filters. When properly integrated, they can work with all other system components (including chassis, passive components and PCB, etc.) to resist internal and external interference. In general, when the cable length is the maximum, the signal received by the equalizer is the minimum. Therefore, the gain and bandwidth of the equalizer should be at the maximum value. However, when the input is not connected and there is no external signal, the gain and bandwidth are also maximum. At maximum gain, even a small amount of harmful EMI or conducted interference will be greatly amplified, affecting the normal operation of the equalizer. Good PCB design can prevent interference and avoid some common equalizer application failures, such as: inability to equalize the maximum cable length at a given data rate; data errors when the cable length is less than the maximum value; false or random output data when the input is open; signal detection error indication.

These failures are caused by: EMI radiation from within the system chassis or on the PCB; noise coupled to the input from logic devices or power supplies through the component mounting pins of the input network; crosstalk from other nearby circuits to the input and/or adaptive equalizer circuit (AEC); coupling from the equalizer input and output circuits. ESD events can severely damage semiconductor devices, especially when they are not protected by conductive packaging materials, and even when the semiconductor devices are mounted on the circuit. Devices used for direct cable interface, such as line drivers and cable equalizers, are designed to the maximum ESD rating. Even so, it is unwise to rely solely on the semiconductor device itself to provide all ESD protection, regardless of its rated ESD protection value. The equalizer input circuit has the advantage of a low impedance path to ground through a termination resistor, which improves ESD tolerance. The components used in the input circuit should have sufficient ESD resistance to cope with the maximum ESD event in the design. With proper selection and design, all circuit components (including chassis, connectors, and PCBs) can provide ESD protection for the equalizer and other interface devices.

Design Methods to Improve Performance

The following design measures can resist electronic interference and improve the overall performance of the equalizer: 1. Isolate or shield the equalizer input network and AEC circuit from external and high-level signals on the card; 2. Use durable input circuit components to suppress ESD events; 3. Use multi-layer PCBs with independent transmission lines and power-ground layers to achieve isolation, shielding and ESD protection; 4. Use thin dielectrics (less than 6 mils) between the power and ground layers to increase inter-layer capacitance and high-frequency attenuation; 5. Use two vias when connecting bypass capacitors, termination resistors, collector load resistors, and VCC and VEE pin pads to the layer; 6. Do not connect multiple VCC and VEE pins to one via, as this may cause noise in the device.

Figure 1 shows the recommended CLC014 equalizer circuit, and Figure 2 shows the corresponding PCB layout. On the PCB board, some measures are taken to isolate the equalizer circuit from harmful signal interference. The copper foil is removed from the power layer under the input network and AEC capacitor to eliminate the path for the power layer noise to couple to the input circuit and AEC circuit. Part of the copper foil (dark shadow line) is removed from all layers to isolate the equalizer circuit. These isolation strips can prevent adjacent circuits from directly contacting the equalizer circuit through the middle layer. In this way, the interference signal must take a long path along the isolation strip to approach the input circuit.

This increases the low-pass filtering effect and improves the ability to attenuate harmful signals. The cable driver used to provide the signal loop-back function is often placed adjacent to the equalizer. The output signal of the cable driver is much stronger than the signal received by the equalizer. The isolation strip helps to isolate the cable driver signal and reduce interference with the equalizer input signal. Around the input circuit is a well-grounded guard (shield) ring to reduce the RFI picked up, as shown in Figure 2a. The guard ring can also be replaced by copper on the outer layer of the PCB, as shown in Figure 2b. The copper must connect all ground layers with a spacing of about 1cm to form an effective shield. The common-mode rejection of the equalizer differential input amplifier and the symmetrical input component layout can also enhance RFI rejection. RFI is a common-mode signal when it is received by both input terminals at the same time. A symmetrical input circuit layout with balanced termination impedance allows the RFI signal to reach both input terminals evenly, so that the common-mode rejection function of the input differential amplifier can eliminate most of the interfering signals.