2440 serial port linux programming, related configuration of S3C2440 serial port communication

The relevant registers for UART configuration are as follows (listed in the order in the s3c2440 manual):

1.ULCONn register: linear control register

Function: Set parity, stop bit, data bit (5-8 bits)

Note: It is generally set to no parity, one stop bit, and 8 data bits, which is often called "8N1". At this time, the register value is 0x3. (bit[6]=0 is normal mode, otherwise it is infrared mode);

2.UCONn register: channel n controller

Function: Select UART clock source, set UART interrupt mode

Note: PCLK, UEXTCLK or FCLK/n can be selected. bit[5]=1 is loopback mode, used for testing; bit[3:2] and bit[1:0] control the transmission and reception modes respectively. Beginners often set it to interrupt request or query mode, bit[3:2 ]=bit[1:0]=01.

3.UFCONn register: FIFO control register

Function: Used to set whether to use FIFO, and set the trigger threshold value of each FIFO, that is, an interrupt will be generated when the amount of data in the sending FIFO is generated, and an interrupt will be generated when the amount of data in the receiving FIFO is received. And each FIFO can be reset by setting the UFCONn register. Reading the UFSTATn register can tell whether each FIFO is full and how much data is in it.

Note: When bit[0]=1, FIFO is enabled, otherwise it is disabled. Beginners do not need to use FIFO

4.UMCONn register: UART MODEM control register

Note: bit[4]=0, AFC is invalid

5.UBRDIVn register: baud rate divisor register

Function: Set baud rate divisor

Note: UBRDIVn=(int)(UART clock/(baud rate*16))-1;

UART clock: PCLK, FCLK/n or UEXTCLK, for example, if the baud rate is 115200bps and the UART clock is 40MHz, then UBRDIVn is:

UBRDIVn=(int)(40000000/(115200*16))-1=(int)(21.7)-1(take the nearest integer)=22-1=21.

5.UTRSTATn register: receive/transmit status register

Function: Display receive/transmit buffer register status

Note: In non-FIFO mode, bit[0]=1 indicates that data has been received; bit[1]=1 indicates that the transmit buffer register is empty. In FIFO mode, for the relevant bits of the UFSTAT register, see the manual for details.

6.UERSTATn register: error status register

Function: Indicates whether various errors occur

Note: Beginners don’t need to pay attention to their status. When they learn in depth, they can check the relevant information.

7.UFSTATn register: FIFO status register

Function: Indicates the relevant status of FIFO

Note: bit[14]=1, indicating that the sending FIFO is full and no more data can be sent temporarily. Bit[6]=0, indicating that there is data in the receiving FIFO (personal understanding, but not very rigorous).

8.UMSTATn register: UART MODEM status register

Note: Beginners can ignore

9.UTXHn register: send cache register

Function: UART will save it to the buffer and automatically send it out

Note: bit[7:0]=send data.

10. URXHn register: receive buffer register

Function: When the UART receives data, the CPU reads this register to obtain the data.

Note: bit[7:0]=receive data;

Note: URXHn and UTXHn are divided into big endian and little endian. Pay attention when defining the register, but generally the little endian method is used.