content:
Write 0x00-0xff to the internal address 0x00-0xff of EEPROM (AT24C02) in sequence, and then read the data.
IIC bus introduction:
IIC (Inter-Integrated Circuit, I2C) bus is a two-wire serial bus developed by PHILIPS, used to connect microprocessors and their peripherals. On the IIC bus, only two lines are needed: serial data line SDA and serial clock line SCL to complete communication.
IIC Key Points
1. The statement to clear the IIC interrupt flag rIICCON&= ~0x10; must be after the read-write register IICDS. The interrupt occurs after the register is read and written.
2. Since the reading speed of EEPROM is not fast, each read and write interrupt requires a short delay function;
3. When reading data from AT24C02A, after sending the slave device address with a read command, AT24C02A will return a slave device address information or slave device memory address information as a response, so be sure to discard the byte after reading it, because it is not the information we want to read;
4. According to the timing of AT24C02A, when sending the slave device address byte, its lowest bit is 0 for writing and 1 for reading. But for s3c2440, this bit does not need to be set manually, that is, it does not matter whether it is 0 or 1, because this bit is automatically set by s3c2440 according to whether it is the master device sending mode or the master device receiving mode. (So 0xa0 is used by default);
EEPROM Introduction
AT24CXX series is an EEPROM with an iic bus interface, which mainly includes AT24C01/02/08/16, etc., and its capacity (bits x page) is 128 x 8/256x 8/1024 x 8/2048 x 8/; for AT24C02A, the three-bit address line is hard-coded, because it is enough to use 8-bit address when performing read and write operations, so the three-bit address line is hard-coded as chip select, and the first bit of the three-bit address line of AT24C02A must be hard-coded, and the last two bits can be used as internal page addresses. Because the size of AT24C02A exceeds 256 bytes, 8 is the addressing, and all the space in the chip cannot be used. Therefore, the last two bits can be determined by the program.
Write data in EEPROM
When writing data, AMR9 acts as the master device and EEPROM acts as the slave device.
The first way to write byte (this is the method used in my program):
Writing a byte actually requires sending data three times. During this process, the master device is in the sending state. The first data is the device address. The second data is the offset of the first address of the EEPROM that the ARM9 wants to write to the data storage.
The first is the address of the first data. The second is the specific data you want to write into the EEPROM. Finally, stop.
The second page writing method:
In fact, writing a page should be consistent with writing a byte. The first data is the device address. The second data is the offset address of the EEPROM that ARM9 wants to write relative to the first address of the data storage (but this address is the first address.
AT24C02 has 8 bytes per page, and AT24C04/08 has 16 bytes per page. So when writing a page, write at most the size of a page. If you write too much, it will start again from the first address, and the previously written will be overwritten. ). Third, fourth, ... data - the data you want to write to the EEPROM. Finally stop
Read data from EEPROM
The master device is still ARM9, the slave device is EEPROM, whether it is sending state or receiving state, this iic will automatically set;
The first method reads the current address data:
The first data - (the master device is now in the generating state) sends the slave device address,
The second data - (the master device is in the receiving state) ARM9 receives data, note that it is NO ACK at this time. Then stop. (Read the data after generating NO ACK. The data will be stable at this time. There is a question on the Internet why when reading IIC
You need to read it twice at the end. I experimented with it myself and only needed the last time.)
The second random reading method: (This method is used in my program)
First data - (Master is in the generating state), send a slave address. The first device address is used for slave matching, also referred to as a "dummy" byte write sequence in the document.
The second data - (the master device is in the generating state), sends an offset address of the data to be read in the EEPROM relative to the first address of the data storage.
The third data - (the master device is in the generating state), send a slave device address. This is a specific request to send this way. (Here the master device will be configured to receive state), this sending device address is used to call
The status of the entire master device.
The fourth data is the data to be read (the master device is in receiving state). It is also a NO ACK, similar to reading the current address. Finally, stop.
The third read sequence address (page read):
The first data - (the master device is in the sending state), sends the device address, and configures the master device to the receiving state. Prepare for the subsequent data reception
The second, third, etc. data - (the master device is in receiving state), each of the previous data will send ACK, and the last data will be a NO ACK. Then stop.
In the above, we should pay attention to the adjustment of the master device status and the processing when it is NO ACK. There is an example program later, which can clearly show how to process it.
Code Blocks
#include "def.h"
#include "2440addr.h"
#include "2440lib.h"
static unsigned int i,j,save_E,save_PE;
static U8 data[256];
static volatile int flag; //Used to identify whether the response signal is received. The flag is cleared to 0 in the terminal processing program
/**********************************************************************
IIC initialization function
******************************************************************/
void iic_init(void){
rGPECON |= 0xa0000000; //GPE15:IICSDA, GPE14:IICSCL (rGPEUP[14:15] has no pull-up option)
//[7]=1 allows the acknowledgement to occur [6]=0 IICCLK = fPCLK /16 PCLK 50MHz, IICCLK = 3.17MHz, Tx Clock = 0.198MHz
// Enable IIC bus Tx/Rx interrupt IICCON[3:0]=16
rIICCON = (1<<7) | (0<<6) | (1<<5) | (0xf);
rIICADD = 0x10; //Slave address indicates the address of 2440 when it is a slave device. Here 2440 exists as a master device, so it has no effect.
rIICSTAT = 0x10; //IIC bus data output enable reading and writing
rIICLC = (1<<2)|(1); // Enable filter delay of five clocks
}
/**********************************************************************
IIC interrupt function
******************************************************************/
void __irq Iic_isr(void)
{
flag = 0;
rSRCPND = 0x1<<27; // Clear interrupt
rINTPND = 0x1<<27;
}
void iic_isr(void){
rINTMSK &= ~(0x1<<27);
pISR_IIC = (unsigned)Iic_isr; //Interrupt entry
}
/**********************************************************************
Write data in EEPROM
******************************************************************/
void Wr24C080(U32 slvAddr, U32 addr, U8 data)
{
flag=1; //The following are all response flags Flag position 1
rIICDS = slvAddr; //**Device address (the address of EEPROM is 1010)
rIICSTAT = 0xf0; // Master device sending mode, write) generates start signal
rIICCON &= ~0x10; //The following are all clear interrupt flags
while(flag == 1) //When the slave address is sent, an ACK signal will be received. Set the flag to 0 in the interrupt processing function
Delay(1);
flag =1 ;
rIICDS = addr; //Offset address
rIICCON &= ~0x10;
while(flag == 1) //When the slave address is sent, an ACK signal will be received. Set the flag to 0 in the interrupt processing function
Delay(1);
flag =1 ;
rIICDS = data; //Specific data to be written
rIICCON &= ~0x10;
while(flag == 1) //When the slave address is sent, an ACK signal will be received. Set the flag to 0 in the interrupt processing function
Delay(1);
rIICSTAT = 0xd0; //Stop MasTx condition
rIICCON = 0xaf; //Resumes IIC operation.
Delay(1);
}
/**********************************************************************
Read data from EEPROM
******************************************************************/
void Rd24C080(U32 slvAddr, U32 addr, U8 *data)
{
unsigned char temp;
flag=1;
rIICDS = slvAddr; //Device address (the address of EEPROM is 1010)
rIICSTAT = 0xf0; // Master device transmission mode is used to send slvAddr and addr, start
rIICCON &= ~0x10;
while(flag == 1) // When the slave address is sent, an ACK signal will be received. Set the flag to 0 in the interrupt processing function
Delay(1);
flag =1 ;
rIICDS = addr; //Offset address
rIICCON &= ~0x10;
while(flag == 1) // When the slave address is sent, an ACK signal will be received. Set the flag to 0 in the interrupt processing function
Delay(1);
flag=1;
rIICDS = slvAddr; //Slave device address. This is a specific request to send. (Here the master device will be configured to receive state),
//This sending device address is used to adjust the status of the main device at the same time.
rIICSTAT = 0xb0; // Master device receiving mode is used to receive data and start
rIICCON &= ~0x10;
while(flag == 1) // When the slave address is sent, an ACK signal will be received. Set the flag to 0 in the interrupt processing function
Delay(1);
// Note: Reading the following byte is necessary because after sending the slave device address with the read command,
// AT24C02A will return a slave device address or slave device memory address as a response, so be sure to discard this byte after reading it, because it is not the information we want to read;
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