Friendly Arm's latest mini2440 study notes - u-boot 1.1.6 transplantation (I)

Starting from this article, I will record the problems encountered by the blogger during the u-boot 1.1.6 porting process. This article will cover two issues:

1. Add development board in u-boot

2. u-boot first stage startup code

1. Add development board in u-boot

1.1. Makefile changes

1.1.1. Add disassembly file output

Line 239 in the Makefile file, the source file is:

ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)

change to:

ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(obj)u-boot.dis $(U_BOOT_NAND)

1.1.2. Adding a development board

Line 1879 of the Makefile file adds the mini2440 development board configuration as follows according to the form of smdk2410:

mini2440_config:unconfig

@$(MKCONFIG) $(@:_config=) arm arm920t mini2440 NULL s3c24x0

1.1.3. Deleting disassembled files during automatic cleanup

Makefile file 2293 lines, source file is:

rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)

change into:

rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(obj)u-boot.dis $(ALL)

1.2. Add header files

Add the mini2440.h file in the include/configs/ directory. You can directly copy a copy of the smdk2410.h file.

1.3. Add core version files

Add the mini2440 directory under the board/directory. You can directly copy the smdk2410 folder.

1.4. Summary

Since then, the mini2440 development board has been added to u-boot 1.1.6. You can directly execute the following command to generate the u-boot.bin file

make mini2440_config

make

But this u-boot.bin file cannot be started, and the relevant code needs to be modified for transplantation.

2. U-boot first stage startup code transplantation

The SOC of mini2440 is S3C2440, and its CPU is an ARM920t core, so the first stage startup code of u-boot is the cpu/arm920t/start.S file.

2.1. Disable watchdog and interrupt service

The watchdog of S3C2440 is the same as that of S3C2410, so make the following changes in the start.S file:

124 lines of source code:

#elif defined(CONFIG_S3C2410)

#define pWTCON 0x53000000

#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */

#define INTSUBMSK 0x4A00001C

#define CLKDIVN 0x4C000014 /* clock divisor register */

change to:

#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)

#define pWTCON 0x53000000 /* watchdog register address */

#define INTMSK 0x4A000008 /* interrupt mask register address */

# define INTSUBMSK 0x4A00001C /* interrupt sub-mask register address */

#define CLKDIVN 0x4C000014 /* clock divisor register */

131 lines of source code:

#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)

ldr r0, =pWTCON

mov r1, #0x0

str r1, [r0]

change to:

#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)

    ldr r0, =pWTCON

    mov r1, #0x0

    str r1, [r0]

142 lines of source code:

# if defined(CONFIG_S3C2410)

ldr r1, =0x3ff

ldr r0, =INTSUBMSK

str r1, [r0]

Then add some code, it becomes:

# if defined(CONFIG_S3C2410)

ldr r1, =0x3ff

ldr r0, =INTSUBMSK

str r1, [r0]

#elif defined(CONFIG_S3C2440)

ldr r1, =0x7FFF

ldr r0, =INTSUBMSK

str r1, [r0]

2.2. Setting MPLL and UPLL

In the source code, find:

/* FCLK:HCLK:PCLK = 1:2:4 */

/* default FCLK is 120 MHz ! */

ldr r0, =CLKDIVN

mov r1, #3

str r1, [r0]

change to:

#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)

/* FCLK:HCLK:PCLK = 1:2:4 */

/* default FCLK is 120 MHz ! */

ldr r0, =CLKDIVN

mov r1, #3

str r1, [r0]

#elif defined(CONFIG_S3C2440)

#define MPLLCON 0x4C000004

#define UPLLCON 0x4C000008

ldr r0, =CLKDIVN

ldr r1, =0x5 /* FCLK:HCLK:PCLK = 1:4:8 */

str r1, [r0]

ldr r0, =MPLLCON

ldr r1, =0x5C011 /* MPLL=400MHz */

str r1, [r0]

ldr r0, =UPLLCON

ldr r1, =0x38022 /* UPLL=48MHz */

str r1, [r0]

/* configure S3C2440 to asynchronous bus mode */

mrc p15, 0, r1, c1, c0, 0

orr r1, r1, #0xc0000000

mcr p15, 0, r1, c1, c0, 0

#endif

2.3. Add NAND boot code

The default in u-boot's smdk2410 code is NOR boot, so you need to add NAND boot code yourself.

Find the NOR startup code in the source file:

#ifndef CONFIG_SKIP_RELOCATE_UBOOT

relocate: /* relocate U-Boot to RAM */

adr r0, _start /* r0 <- current position of code */

ldr r1, _TEXT_BASE /* test if we run from flash or RAM */

cmp r0, r1 /* don't reloc during debug */

beq stack_setup

ldr r2, _armboot_start

ldr r3, _bss_start

sub r2, r3, r2 /* r2 <- size of armboot */

add r2, r0, r2 /* r2 <- source end address */

copy_loop:

ldmia r0!, {r3-r10} /* copy from source address [r0] */

stmia r1!, {r3-r10} /* copy to target address [r1] */

cmp r0, r2 /* until source end addreee [r2] */

ble copy_loop

#endif /* CONFIG_SKIP_RELOCATE_UBOOT */

change to:

#ifndef CONFIG_SKIP_RELOCATE_UBOOT

relocate: /* relocate U-Boot to RAM */

adr r0, _start /* r0 <- current position of code */

ldr r1, _TEXT_BASE /* test if we run from flash or RAM */

cmp r0, r1 /* don't reloc during debug */

beq stack_setup

#if defined(CONFIG_NOR_BOOT)

ldr r2, _armboot_start

ldr r3, _bss_start

sub r2, r3, r2 /* r2 <- size of armboot */

add r2, r0, r2 /* r2 <- source end address */

copy_loop:

ldmia r0!, {r3-r10} /* copy from source address [r0] */

stmia r1!, {r3-r10} /* copy to target address [r1] */

cmp r0, r2 /* until source end addreee [r2] */

ble copy_loop

#elif defined(CONFIG_NAND_BOOT)

ldr sp, =0x1000 /* setup stack to 4k temporarily to call the c function nand_read_ll*/

bl nand_init_ll /* initialize nand flash */

ldr r0, _TEXT_BASE /* destination for u-boot relocation */

ldr r1, =0x0 /* ​​source address in NAND */

ldr r2, =0x40000 /* length to read from NAND to SDRAM, 256K */

bl nand_read_ll /* call nand_read_ll to relocate u-boot */

#endif

#endif /* CONFIG_SKIP_RELOCATE_UBOOT */

2.4. Summary

So far, all the codes in start.S have been modified.

3. Description

The last part involves two functions, nand_init_ll and nand_read_ll. There are many C codes for these two functions used in NAND startup on the Internet, but the blogger reported errors after downloading them. Finally, I made up my mind and modified a version based on the NAND bare metal program of the great Wei Dongshan, and the effect was good.