STM8->EXTI

Interrupts, especially external interrupts, are an important means for MCU to implement complex functions.

Interrupt sources and vectors:

    All I/O pins have external interrupt capability, and each port has an independent interrupt vector and independent flag.

    Interrupts of various functional peripherals

    Up to 32 interrupt vectors (entry addresses are fixed by hardware), up to 40 external interrupt sources (4 levels of programmable software nesting priority), 11 of which are assigned as external interrupts.

Priority and response logic:

    Reset has the highest priority and all interrupts are disabled during reset.

There can be several interrupts queued for processing at the same time:

1. The interrupt with the highest software priority is responded to; (the software priority of each interrupt is configured through ITC->SPRx registers I1 and I0)

2. If several queued interrupts have the same software priority, the interrupt with the highest hardware priority is responded to first. //The hardware priority of the interrupt is unique and mutually exclusive

    Hardware interrupt priority low->high: MAIN, IT4, IT3, IT2, IT1, IT0, TRAP and RESET. Interrupt masking can be achieved through bits I1 and I0 of the CC register and ITC->SPRx to set the software priority. PD7 is the highest priority hardware interrupt source TLI entry.

Management of interruptions

1. All priorities in concurrent interrupt management mode are level 3, except for responding to RESET, TRAP, and TLI interrupts, which cannot be interrupted;

2. The nested interrupt management mode allows interrupts to be responded to in the interrupt program; this mode becomes effective immediately once the priority of an interrupt is lower than level 3;

Use the interrupt controller ITC to manage each interrupt:

    Non-maskable events: RESET, TRAP; non-maskable highest priority hardware interrupt TLI

    Non-maskable interrupts: RESET, TLI and TRAP have the highest software priority to handle, regardless of the status of I1 and I0 of the CC register.

    The TRAP instruction is prohibited in the TLI interrupt service subroutine. The TLI interrupt can interrupt (except TRAP and RESET) level 3 software interrupts. The software interrupt TRAP cannot cause the processor to exit from the Halt mode.

Configuration and use of simple interrupts (taking STM8L151 as an example):

    GPIO_Init(KEY_PORT, KEY_Pin, GPIO_Mode_In_FL_IT);

    EXTI_DeInit(); 

    EXTI_SetPinSensitivity(EXTI_Pin_4,EXTI_Trigger_Falling);

If you use registers to configure interrupts:

Register EXTI->CR1 function definition

Register EXTI->CR2 function definition

Enable interrupt

    {asm("rim"); }== {enableInterrupts();}

The definition of interrupt in the stm8l15x.h file is as follows:

 #define enableInterrupts() __enable_interrupt() /* enable interrupts */

 #define disableInterrupts() __disable_interrupt() /* disable interrupts */

 #define rim() __enable_interrupt() /* enable interrupts */

 #define sim() __disable_interrupt() /* disable interrupts */

Detailed 32 interrupt vector definitions:

#define FLASH_EOP_vector 0x03

#define FLASH_WR_PG_DIS_vector 0x03

#define DMA1_CH0_HT_vector 0x04

#define DMA1_CH0_TC_vector 0x04

#define DMA1_CH1_HT_vector 0x04

#define DMA1_CH1_TC_vector 0x04

#define DMA1_CH2_HT_vector 0x05

#define DMA1_CH2_TC_vector 0x05

#define DMA1_CH3_HT_vector 0x05

#define DMA1_CH3_TC_vector 0x05

#define RTC_ALARM_vector 0x06

#define RTC_WAKEUP_vector 0x06

#define EXTIE_vector 0x07

#define EXTIF_vector 0x07

#define EXTIPVD_vector 0x07

#define EXTIB_vector 0x08

#define EXTID_vector 0x09

#define EXTI0_vector 0x0A

#define EXTI1_vector 0x0B

#define EXTI2_vector 0x0C

#define EXTI3_vector 0x0D

#define EXTI4_vector 0x0E

#define EXTI5_vector 0x0F

#define EXTI6_vector 0x10

#define EXTI7_vector 0x11

#define CLK_CSS_vector 0x13

#define CLK_SWITCH_vector 0x13

#define TIM1_BIF_vector 0x13

#define COMP_EF1_vector 0x14

#define COMP_EF2_vector 0x14

#define TIM2_OVR_UIF_vector 0x15

#define TIM2_CAPCOM_BIF_vector 0x16

#define TIM2_CAPCOM_CC1IF_vector 0x16

#define TIM2_CAPCOM_CC2IF_vector 0x16

#define TIM2_CAPCOM_TIF_vector 0x16

#define TIM3_OVR_UIF_vector 0x17

#define TIM3_CAPCOM_BIF_vector 0x18

#define TIM3_CAPCOM_CC1IF_vector 0x18

#define TIM3_CAPCOM_CC2IF_vector 0x18

#define TIM3_CAPCOM_TIF_vector 0x18

#define TIM1_OVR_UIF_vector 0x19

#define TIM1_CAPCOM_CC1IF_vector 0x1A

#define TIM1_CAPCOM_CC2IF_vector 0x1A

#define TIM1_CAPCOM_CC3IF_vector 0x1A

#define TIM1_CAPCOM_CC4IF_vector 0x1A

#define TIM1_CAPCOM_COMIF_vector 0x1A

#define TIM1_CAPCOM_TIF_vector 0x1A

#define TIM4_TIF_vector 0x1B

#define TIM4_UIF_vector 0x1B

#define SPI_MODF_vector 0x1C

#define SPI_OVR_vector 0x1C

#define SPI_RXNE_vector 0x1C

#define SPI_TXE_vector 0x1C

#define SPI_WKUP_vector 0x1C

#define USART_T_TC_vector 0x1D

#define USART_T_TXE_vector 0x1D

#define USART_R_IDLE_vector 0x1E

#define USART_R_OR_vector 0x1E

#define USART_R_PE_vector 0x1E

#define USART_R_RXNE_vector 0x1E

#define I2C_ADD10_vector 0x1F

#define I2C_ADDR_vector 0x1F

#define I2C_AF_vector 0x1F

#define I2C_ARLO_vector 0x1F

#define I2C_BERR_vector 0x1F

#define I2C_BTF_vector 0x1F

#define I2C_OVR_vector 0x1F

#define I2C_RXNE_vector 0x1F

#define I2C_SB_vector 0x1F

#define I2C_STOPF_vector 0x1F

#define I2C_TXE_vector 0x1F

#define I2C_WUFH_vector 0x1F