Parallel expansion and interface design of I2C interface of 8051 microcontroller

    1 Introduction

    I2C bus interface devices are widely used in video processing, mobile communications and other fields. In addition, general I2C bus interface devices, such as RAM, ROM, A/D, D/A, LCD driver with I2C bus, are also increasingly used in computers and automatic control systems. With the increasing application of I2C interface devices, the communication between 8051 series microcontrollers and them is becoming more and more frequent.

    When the 8051 series microcontroller communicates with the I2C bus interface device, the general port of the 8051 is connected to the SCL and SDA of the I2C bus device. According to the I2C bus data transmission protocol, the 8051 must frequently set and clear its two general ports. According to the assembly program compiled based on the 51 instruction system, it takes 9 machine cycles to transmit one bit of data, while for the 8051, one machine cycle takes 6 clock cycles, that is, 54 clock cycles are used to transmit one bit of data. This greatly occupies the CPU's working time, reduces the system's working efficiency, and makes it difficult for the advantages of the I2C device to appear. Therefore, it is necessary to design a dedicated interface circuit between the 8051 and the I2C bus. The interface circuit can automatically send and receive data on the I2C bus, and the CPU only needs to access the relevant registers in the interface circuit through the parallel port to achieve data exchange with the I2C device, thereby improving the performance of the entire system. This design uses VHDL hardware description language as the tool, and uses ALTERA's MAXPLUSⅡ software for compilation and simulation. The downloaded chip is EPM7128SLC84-15.

    2 Design goals and requirements

    In order to increase the speed of data transmission, an I2C interface circuit is designed. 8051 does not exchange data with I2C devices directly, but exchanges data with the I2C interface circuit through the parallel port. Data transmission on the I2C bus is also completed through the I2C interface circuit. Therefore, data exchange with I2C devices can be achieved through the CPU's external memory read and write instructions, so that the operation of the serial port can be achieved in the way of the parallel port.

    There is a control register CI0 and a data register CI1 inside the I2C interface circuit, that is, the I2C interface circuit occupies two addresses. The I2C interface circuit is programmed by writing the content of the control register CI0, and the data exchange with the I2C device is realized by reading and writing the content of the data register CI1. The content in CI0 defines the type of operation (read or write) of the 8051 on the I2C device and the number of bytes of the address in the I2C device, so that the I2C interface circuit can identify whether the data transmitted from the 8051 is an address or data, whether the 8051 is going to send data or receive data, and the length of the data.

    If 8051 wants to send data to the I2C device, according to the I2C bus protocol, the I2C bus is started after data CI1 receives the first data, and then the data in CI1 is converted from parallel to serial and sent out bit by bit. After sending, a flag is set to let 8051 know that it can send the next bus. After that, the address in the I2C device is first written, and then data is received. After serial-to-parallel conversion, the received data is loaded into CI1, and then the flag is set to let 8051 know that the data can be read.

    According to the above design requirements, the pins of the I2C interface chip are shown in Figure 1. Among them, clk can use an independent clock, so that the bit transmission speed of the I2C bus is much higher than the bit operation of 8051, so that the data transmission of the I2C bus can be close to the data rate of the parallel port; a0 is the address signal input, when a0=0, CI0 write operation is performed, when a0=1, CI1 read/write operation is performed; bz is the flag output bit, when bz=0, 8051 needs to wait, when bz=1, 8051 can operate CI1.

    The situation of the I2C interface chip in the system is shown in Figure 2. Here, 8051 uses the query mode to operate the I2C interface chip, and it can also use the interrupt mode instead.

    3 Implementation of Parallel Interface Design

    3.1 Internal structure of interface design

    The internal structure of the chip is shown in Figure 3. The system consists of 6 parts: control register CI0, data register CI1, parallel-to-serial conversion, serial-to-parallel conversion, shift register and I2C control module.

    3.2 Mode Control Word

    8051 writes control words to the control register CI0 to implement programmable control of the I2C interface. The control word format of CI0 is as follows:

    A2, A1, A0 bits: Chip select (device address) for the I2C device group connected to the 8051. Different device communications are selected when corresponding to different values.

    R/W: Used to control the read and write operations of 8051 to I2C devices. 1 means 8051 reads data from I2C devices; 0 means 8051 writes data to I2C devices.

    M1M0: 4 working modes when S=1:

    ①The I2C bus is not connected and a write operation is required.

    ②The I2C bus is not connected and a read operation is required.

    ③The I2C bus is connected. Change an I2C device or a new address and perform a write operation.

    ④The I2C bus is connected. Change an I2C device or a new address and perform a read operation.

    S: working control bit. When S＝0, the I2C bus is turned off, otherwise S＝1.

    DZS: Indicates the address number that 8051 reads and writes to the I2C device. Specifically:

    0: 8051 reads and writes single-byte addresses within the I2C device.

    1: 8051 reads and writes double-byte addresses within the I2C device.

    3.3 Implementation of I2C transmission protocol by I2C module

    According to the I2C data transmission protocol, when the clock is high , the data line jumps from high to low, starting I2C data transmission. Then, for each clock pulse, one bit of serial data is transmitted. After the eighth pulse arrives, one byte of transmission is completed. When the ninth pulse arrives, an acknowledgement signal is sent. When writing data, the I2C device receives the data and sends an acknowledgement signal; when reading data, the 8051 receives the data and sends an acknowledgement signal. During the data transmission process, the content on the data line remains unchanged while the clock is high. After the data transmission is completed and the acknowledgement is completed, a stop signal is needed to stop the data transmission. When the clock is high, the data line jumps from low to high to implement this stop signal.

    The I2C module implements the I2C data transmission protocol. When the start signal is 1, data transmission is started; when the write signal is 1, data is written to the I2C device; when the read signal is 1, data is read from the I2C device.

    During the reading and writing process, the output flag flag and counter dcnt control the two-bit vector of en, thereby controlling the parallel-to-serial conversion register and the serial-to-parallel conversion register's merge, shift, hold, and clear operations. When the stop signal is 1, the data transmission ends.

    3.4 Working principle and control process of interface chip

    8051 writes control words to the control register CI0 to implement programming control of the I2C interface; writes data to the data register CI1 to implement data transmission on the I2C interface.

    When bz=1, 8051 reads and writes the data register, and the interface circuit automatically sets bz to 0 after each read and write. When the interface circuit completes the relevant operations and waits for 8051 to read and write, it sets bz to 1.

    (1) The I2C bus is not connected and a write operation is required. Operation of 8051:

    ① Write control word W1; ② When bz=1, write the first byte of the address in the device; ③ When bz=1, write the second byte of the address in the device...; ④ When bz=1, write the first byte...

    I2C Operation:

    After receiving the control word W1, the operations are as follows: ① set bz=1 to start the I2C bus; ② send the first byte (device selection, write) according to the device address in the control word; ③ send the address inside the device, set bz=1; ④ send the data content, set bz=1...

    (2) The I2C bus is not connected and a read operation is required. Operation of 8051:

    ① The circuit writes the control word W2; ② Writes the first byte of the address in the device; ③ When bz=1, writes the second byte of the address in the device...; ④ When bz=1, reads the first byte...

    I2C Operation:

    After receiving the control word W2, the operations are as follows: ① set bz=1 to start the I2C bus; ② output the first byte (device selection, write) according to the device address in the control word; ③ send the address inside the device; ④ close the I2C bus; ⑤ start the I2C bus; ⑥ send the device selection byte for the second time, read; ⑦ receive the data content, set bz=1...

    (3) The I2C bus is connected. Change the I2C device or change the address to a new one and perform a write operation.

    Operation of 8051:

    ① Write control word W5; ② When bz=1, write the first byte of the address inside the device; ③ When bz=1, write the second byte of the address inside the device...; ④ When bz=1, write the first byte...

    I2C Operation:

    After receiving the control word W5, the operations are as follows: ① set bz=1 to close the I2C bus; ② start the I2C bus; ③ send the first byte (device selection, write) according to the device address in the control word; ④ send the device internal address and set bz=1.

    (4) The I2C bus is connected. Change the I2C device or change the address to a new one and perform a read operation.

    Operation of 8051:

    ① The circuit writes the control word W6; ② Writes the first byte of the address in the device; ③ When bz=1, writes the second byte of the address in the device...; ④ When bz=1, reads the first byte...

    I2C Operation:

    After receiving the control word W6, the operations are as follows: ① set bz=1 to close the I2C bus; ② start the I2C bus; ③ send the first byte (device selection, write) according to the device address in the control word; ④ send the address inside the device; ⑤ close the I2C bus; ⑥ start the I2C bus; ⑦ send the device selection byte for the second time, read; ⑧ receive the data content, set bz=1...

    4 Conclusion

    The design of the expansion interface chip is implemented in VHDL language. All the programs of the chip design are compiled by ALTERA's MAXPLUSⅡ software, and the simulation results are correct. The compiled and simulated VHDL program is downloaded to the EPM7128SLC84-15 chip via the download line and verified to be correct. The interface clock of the design requires 6 MHz, which can be directly connected to the microcontroller interface.

    After the expansion, it only takes 4 clock cycles to transmit one bit of data. With the expansion, the clock for accessing the I2C device can be set by itself, and the communication between them does not need to wait for 8051. Once the parallel data of 8051 is sent out, the interface can immediately transmit at the speed set by itself. Therefore, when the interface communicates between 8051 and I2C devices, the data transmission can reach the parallel speed, which is the biggest advantage of this interface expansion design.

    Since the design software used is ALTERA's MAXPLUSⅡ software, the downloaded simulation chip is EPM7128SLC84, the chip delay time is 15 s, the delay time is too long; the interface design itself can further reduce the clock of data transmission, and further improve the speed of data transmission. Based on the above two points, this design needs to be further optimized in order to further improve performance and speed.

    references

    ［1］He Liming．I2C Bus Application System Design［M］．Beijing: Beijing University of Aeronautics and Astronautics Press, 1995．

    ［2］ Zeng Fantai, Chen Meijin. VHDL Programming［M］. Beijing: Tsinghua University Press, 2002.