MSP430 Register Chinese Notes ---- Serial Port Register

/************************************************************
* The bits defined by USART serial port registers "UCTL", "UTCTL", and "URCTL" are shared by serial port 1 and serial port 2
**********************************************************/
/* UCTL serial port control register*/ 
#define PENA 0x80 /*Parity enable bit*/
#define PEV 0x40 /*Even parity, odd parity when 0*/
#define SPB 0x20 /*Stop bit is 2, stop bit is 1 when 0*/
#define CHAR 0x10 /*Data bit is 8, data bit is 7 when 0*/
#define LISTEN 0x08 /*Self-loop mode (sending data and receiving the sent data at the same time)*/
#define SYNC 0x04 /*Synchronous mode, asynchronous mode when 0*/
#define MM 0x02 /*Address bit multi-machine protocol (asynchronous) when 1 Master mode (synchronous); when it is 0, the line is idle and the multi-machine protocol (asynchronous) Slave mode (synchronous) */
#define SWRST 0x01 /*Control bit*/

/* UTCTL serial port transmission control register*/
#define CKPH 0x80 /*When the clock phase control bit (only used in synchronous mode) is 1, the clock UCLK delays half a cycle*/   
#define CKPL 0x40 /*When the clock polarity control bit is 1, the asynchronous is opposite to UCLK; the synchronous falling delay is valid*/
#define SSEL1 0x20 /*Clock source selection bit: combined with SSEL0, there are four modes: 0, 1, 2, and 3*/
#define SSEL0 0x10 /*"0" selects external clock, "1" selects auxiliary clock, "2", "3" selects system subclock*/
#define URXSE 0x08 /*Receive trigger delay control bit (only used in asynchronous mode)*/
#define TXWAKE 0x04 /*Multi-processor communication transmission control bit (only used in asynchronous mode)*/
#define STC 0x02 /*External pin STE selection bit is 0 for 4-wire mode and 1 for 3-wire mode*/
#define TXEPT 0x01 /*Transmitter empty flag*/

/* URCTL serial port receive control register. In synchronous mode, only two bits are used: FE and OE*/
#define FE 0x80 /*Frame error flag*/          
#define PE 0x40 /*Parity error flag*/
#define OE 0x20 /*Overflow flag*/
#define BRK 0x10 /*Break detection bit*/
#define URXEIE 0x08 /*Receive error interrupt enable bit*/
#define URXWIE 0x04 /*Receive wake-up interrupt enable bit*/
#define RXWAKE 0x02 /*Receive wake-up detection bit*/
#define RXERR 0x01 /*Receive error flag*/

/****************************************************************
* USART 0 serial port 0 register definition
************************************************************/

#define U0CTL_              0x0070  /* UART 0 Control */
sfrb    U0CTL             = U0CTL_;
#define U0TCTL_             0x0071  /* UART 0 Transmit Control */
sfrb    U0TCTL            = U0TCTL_;
#define U0RCTL_             0x0072  /* UART 0 Receive Control */
sfrb    U0RCTL            = U0RCTL_;
#define U0MCTL_             0x0073  /* UART 0 Modulation Control */
sfrb    U0MCTL            = U0MCTL_;
#define U0BR0_              0x0074  /* UART 0 Baud Rate 0 */
sfrb    U0BR0             = U0BR0_;
#define U0BR1_              0x0075  /* UART 0 Baud Rate 1 */
sfrb    U0BR1             = U0BR1_;
#define U0RXBUF_            0x0076  /* UART 0 Receive Buffer */
const sfrb U0RXBUF        = U0RXBUF_;
#define U0TXBUF_            0x0077  /* UART 0 Transmit Buffer */
sfrb    U0TXBUF           = U0TXBUF_;

/* Alternate register names */

#define UCTL0_              0x0070  /* UART 0 Control */
sfrb    UCTL0             = UCTL0_;
#define UTCTL0_             0x0071  /* UART 0 Transmit Control */
sfrb    UTCTL0            = UTCTL0_;
#define URCTL0_             0x0072  /* UART 0 Receive Control */
sfrb    URCTL0            = URCTL0_;
#define UMCTL0_             0x0073  /* UART 0 Modulation Control */
sfrb    UMCTL0            = UMCTL0_;
#define UBR00_              0x0074  /* UART 0 Baud Rate 0 */
sfrb    UBR00             = UBR00_;
#define UBR10_              0x0075  /* UART 0 Baud Rate 1 */
sfrb    UBR10             = UBR10_;
#define RXBUF0_             0x0076  /* UART 0 Receive Buffer */
const sfrb RXBUF0         = RXBUF0_;
#define TXBUF0_             0x0077  /* UART 0 Transmit Buffer */
sfrb    TXBUF0            = TXBUF0_;

#define UCTL_0_             0x0070  /* UART 0 Control */
sfrb    UCTL_0            = UCTL_0_;
#define UTCTL_0_            0x0071  /* UART 0 Transmit Control */
sfrb    UTCTL_0           = UTCTL_0_;
#define URCTL_0_            0x0072  /* UART 0 Receive Control */
sfrb    URCTL_0           = URCTL_0_;
#define UMCTL_0_            0x0073  /* UART 0 Modulation Control */
sfrb    UMCTL_0           = UMCTL_0_;
#define UBR0_0_             0x0074  /* UART 0 Baud Rate 0 */
sfrb    UBR0_0            = UBR0_0_;
#define UBR1_0_             0x0075  /* UART 0 Baud Rate 1 */
sfrb    UBR1_0            = UBR1_0_;
#define RXBUF_0_            0x0076  /* UART 0 Receive Buffer */
const sfrb RXBUF_0        = RXBUF_0_;
#define TXBUF_0_            0x0077  /* UART 0 Transmit Buffer */
sfrb    TXBUF_0           = TXBUF_0_;

/****************************************************************
* USART 1 serial port 1 register definition
************************************************************/

#define U1CTL_              0x0078  /* UART 1 Control */
sfrb    U1CTL             = U1CTL_;
#define U1TCTL_             0x0079  /* UART 1 Transmit Control */
sfrb    U1TCTL            = U1TCTL_;
#define U1RCTL_             0x007A  /* UART 1 Receive Control */
sfrb    U1RCTL            = U1RCTL_;
#define U1MCTL_             0x007B  /* UART 1 Modulation Control */
sfrb    U1MCTL            = U1MCTL_;
#define U1BR0_              0x007C  /* UART 1 Baud Rate 0 */
sfrb    U1BR0             = U1BR0_;
#define U1BR1_              0x007D  /* UART 1 Baud Rate 1 */
sfrb    U1BR1             = U1BR1_;
#define U1RXBUF_            0x007E  /* UART 1 Receive Buffer */
const sfrb U1RXBUF        = U1RXBUF_;
#define U1TXBUF_            0x007F  /* UART 1 Transmit Buffer */
sfrb    U1TXBUF           = U1TXBUF_;

#define UCTL1_              0x0078  /* UART 1 Control */
sfrb    UCTL1             = UCTL1_;
#define UTCTL1_             0x0079  /* UART 1 Transmit Control */
sfrb    UTCTL1            = UTCTL1_;
#define URCTL1_             0x007A  /* UART 1 Receive Control */
sfrb    URCTL1            = URCTL1_;
#define UMCTL1_             0x007B  /* UART 1 Modulation Control */
sfrb    UMCTL1            = UMCTL1_;
#define UBR01_               0x007C  /* UART 1 Baud Rate 0 */
sfrb    UBR01             = UBR01_;
#define UBR11_              0x007D  /* UART 1 Baud Rate 1 */
sfrb    UBR11             = UBR11_;
#define RXBUF1_             0x007E  /* UART 1 Receive Buffer */
const sfrb RXBUF1         = RXBUF1_;
#define TXBUF1_             0x007F  /* UART 1 Transmit Buffer */
sfrb    TXBUF1            = TXBUF1_;

#define UCTL_1_             0x0078  /* UART 1 Control */
sfrb    UCTL_1            = UCTL_1_;
#define UTCTL_1_            0x0079  /* UART 1 Transmit Control */
sfrb    UTCTL_1           = UTCTL_1_;
#define URCTL_1_            0x007A  /* UART 1 Receive Control */
sfrb    URCTL_1           = URCTL_1_;
#define UMCTL_1_            0x007B  /* UART 1 Modulation Control */
sfrb    UMCTL_1           = UMCTL_1_;
#define UBR0_1_             0x007C  /* UART 1 Baud Rate 0 */
sfrb    UBR0_1            = UBR0_1_;
#define UBR1_1_             0x007D  /* UART 1 Baud Rate 1 */
sfrb    UBR1_1            = UBR1_1_;
#define RXBUF_1_            0x007E  /* UART 1 Receive Buffer */
const sfrb RXBUF_1        = RXBUF_1_;
#define TXBUF_1_            0x007F  /* UART 1 Transmit Buffer */
sfrb    TXBUF_1           = TXBUF_1_;