PCIE jitter test problem analysis and solutions

Project background: The project is a cloud computing product. All high-speed and low-speed signals must be tested for signal integrity, including high-speed serial signals PCI-Express Gen1 (referred to as PCIe Gen1). The PCIe Gen1 signal is divided into two situations: CEM and base. The CEM test can be directly tested using the fixture of the PCI-sig Association; the base test directly uses the probe to detect the test point of the final end. This will bring about a problem, how to Test the final end of the chip? Because the signal interconnection channel not only includes PCB traces, but also includes the wiring inside the chip. Generally, we think that the measured Die inside the chip is the final end.

The PCIE 1.0 of this project belongs to PCIe base and interconnects the CPU and Ethernet PHY, as shown in Figure 1 below:

Figure 1 Schematic diagram

Therefore, during testing, the probe needs to be detected to the final end. However, for current oscilloscope testing, it can only test the pins of the chip, and there is no way to detect the Die of the final end, as shown in Figure 2 below.

Figure 2 The test point can only detect the pins of the chip

Test equipment: oscilloscope (16GHz), test probe (16GHz), multimeter, soldering iron, calibration board, network analyzer (with TDR option)

Analysis software: Intel Sigtest

Problem description and analysis: When testing the signal at the receiving end (RX), the Ethernet PHY sends the signal. The test point is selected on the via hole below the CPU BGA. There is no problem with the signal. The eye diagram and jitter can meet the requirements of the PCI-sig Association. specification. When testing the transmitter (TX), the CPU sends signals and the Ethernet PHY is the receiver. Since the PHY chip package is QFP, the probe is pointed at the pin. After obtaining the test waveform, analyze the waveform in the analysis software and it can pass the eye diagram template test specification, but it is found that the jitter cannot pass the specification, even if the test is repeated several times. Calibrated the oscilloscope and test probe again and tested again, still the same. The results obtained each time are shown in Figure 3 below:

Figure 3 Eye diagram and jitter test

The result shows fail, and it is jitter fail. Jitter problems are generally more troublesome. From the eye diagram, the trajectory of the eye diagram is very sparse and not very smooth.

Expand the original waveform of the oscilloscope and observe it, and find that the signal has non-monotonic phenomena on the rising and falling edges. Comparing the eye diagram, it just corresponds to the intersection of the upper eye diagram, as shown in Figure 4 below.

Figure 4 Test waveform diagram

Generally, nonmonotonicity is caused by impedance discontinuities. After the PCB production was completed, we conducted an impedance test on the high-speed signal. The corresponding impedance is shown in Figure 5 below:

Figure 5 Impedance test curve

As shown in the picture above, this is the result obtained by using the TDR software test of the network analyzer. The design impedance of the signal line is 85ohm, as shown in the red box curve in Figure 5 above. The test impedance can meet the requirement within 85ohm +/-10 Design requirements, it can be considered that its impedance consistency is relatively good. There is no problem of signal line impedance mutation. If there is no sudden change in impedance, this non-monotonic situation usually occurs during testing. Most of the time it is caused by the test not being at the final end (of course, if the die at the final end cannot be reached, then at least the stub must be the shortest).

The Ethernet PHY package used in the project is shown in Figure 6 below:

Figure 6 Chip packaging

In this kind of package, the internal wiring of the chip is often relatively long. When testing, the detection point is on the pin of the chip, so the internal wiring is a section of stub. Obviously, this section of stub is very long. Due to the The effect may eventually lead to non-monotonic signal waveforms during testing. This in turn affects the performance of signal integrity such as eye diagram and jitter.

Solution: After analyzing the related reasons, it is suspected that the wiring inside the chip formed a stub during the test. Then remove the chip during the test and solder 50ohm termination resistors on the two PCIE signal pins, similar to PCIE The test of CEM is the same. The probe is connected to the resistor end for testing, so that there will be no stub. If the signal waveform is good and can meet the eye diagram, jitter and other performance indicators, then it is suspected that the stub is caused by the wiring inside the chip. Reflection, this is established. In this case, it can be considered that the signal integrity performance of the PCIe interconnect channel meets the product and specification requirements.

After removing the chip, connect the resistor to the terminal, and obtain the eye diagram and jitter analysis results as shown in Figure 7 below:

Figure 7 Test eye diagram and jitter after changes

Figure 8 below is the expanded waveform after termination. No non-monotonicity is observed at either the rising or falling edges.

Figure 8 Test waveform after change

To sum up, the problem of PCIe Gen1 test signal integrity failure here is caused by the test point not being tested at the final end. It can be inferred that there is no problem with the signal integrity of this PCIe interconnection channel.

The same is true if other tests encounter this situation, especially if the chips of some projects are very large, such as FPGA. If the signal line that needs to be tested can detect the test point far away from the final terminal (Die), during the test When a problem occurs again, you need to consider whether it is caused by the test point not being at the final end (or closest to the final end).