Application of portable amplitude-frequency characteristic tester based on 51 core and FPGA device

The Core Generator tool provided by Xilinx is used to initialize and configure the three storage areas DATA, XDATA and CODE used by the IP core. The size of the storage area is determined by the storage resources consumed by the C language program and the total size of the Block Memory resources inside the FPGA. The data width of all storage areas in this system is set to 8 bits, and the address signal width corresponding to each storage area is 7 bits, 11 bits and 14 bits. The CODE area is configured as read-only mode (Read Only) to store the instruction code of the 51 core and load the generated .coe file. The design process of the 51 core is completed through synthesis, translation, mapping, layout and routing, and generation of programming files [3].

Implementing the display control and data decoding display of color screen LCD in the 51 core can greatly reduce the difficulty caused by the complex initialization timing of the color screen and the inflexibility of FPGA in the design of human-computer interaction interface [4]. At the same time, the use of C code to operate the LCD screen has wide versatility and scalability. When the LCD model changes, the display control can be realized by slightly modifying the initialization control word.

3.2 Peak Detection Module

The system uses software programming to realize the peak detection function. First, the frequency sweep interval is divided into equal parts, the signal peaks at the divided points are measured one by one, and the calculated gains are stored in the FIFO. When a scan is completed, the amplitude-frequency characteristic data of the system can be obtained.

Before measuring the signal's maximum voltage, since the signal is easily disturbed, the possibility of signal jitter cannot be ruled out. For this reason, a simple filter is used to smooth the signal before measurement to reduce the error of the maximum measurement. The averaging method is used here. The input signal is sequentially taken and saved to form a new signal, the signal voltage of which is obtained by taking the average of the sum of the voltage obtained by the first two clocks of the original input signal and the voltage obtained by the last two clocks. After the signal is simply smoothed, the new signal generated is used as the reference signal for the maximum measurement. After signal shaping, a standard square wave signal is obtained, and one cycle of the signal corresponds to two cycles of the input signal, where the high level and the low level each correspond to one cycle.

The peak-to-peak value of the signal voltage is the maximum value minus the minimum value. However, after the signal is quantized by the A/D converter, the value obtained is a 12-bit code, which is expanded to a 16-bit code. "1111111111111111" indicates a voltage of 2 V, and "10000000000000000" indicates a voltage of 0

V, "00000000000000000" means the voltage is -2 V. If the maximum and minimum values ​​are directly subtracted, the result will be wrong. Therefore, the method of first converting the minimum value (negative voltage) into the corresponding positive voltage is adopted, that is:

Among them, B represents the minimum value, A represents the corresponding positive voltage value, and then the corresponding positive voltage value is added to the maximum value, which is the peak-to-peak value of the signal voltage.

3.3 Asynchronous FIFO Design

The data rate of A/D data acquisition is very high. In this paper, the system clock is 40 MHz, and the acquisition data width is 12 bits. In this way, the amount of data collected per second is 40 M×12 bit/8=60 MB/s. Such a high-speed data flow far exceeds the processing capacity of the 51 core. In order to ensure the validity and reliability of the data read by the 51 core, an asynchronous FIFO is used in the system to cache the data. The design of FIFO is realized by configuring the Block RAM resources inside the FPGA [5, 6]. In order to achieve the purpose of simultaneous acquisition and display, two identical FIFOs are configured, both of which are 512×8 bits in size. Under the control of the read and write clocks, by setting the read enable and write enable signals, at the same time, one FIFO is always performing a write operation, while the other FIFO reads out the full data. For the same FIFO, the read and write signals are not allowed to be valid at the same time, so that the reception and reading of A/D data and handing it over to the 51 core for processing can be carried out simultaneously, thereby ensuring the continuity of data transmission.

4 System debugging and testing

After completing the hardware and software design of the system, debugging and testing are required. During the test, a first-order LC low-pass filter network is used. From the obtained frequency characteristic curve, it can be seen that the system main interface displays stably and has rich color information. When switching to the system status setting or test information display interface, the sweep frequency range, step value, sweep time and other parameters of the excitation signal can be set. At the same time, the gain corresponding to each frequency point can be queried by inputting the frequency point by keystroke, and the test accuracy is relatively high.

The system realizes the overall design of a portable amplitude-frequency characteristic tester based on the platform of FPGA and 51 core. The core modules in the design are debugged, such as 51 core, TFT-LCD liquid crystal, asynchronous FIFO, etc. The test shows that the system works stably, has high measurement accuracy, strong real-time performance, and a simple hardware circuit structure. At present, the system has been applied to the amplitude-frequency characteristic test of a certain type of transformer winding, and has achieved good test results. This paper breaks the 51 core research aimed at timing simulation and functional verification, and reasonably applies the 51 core to the electronic system design example, and has achieved success, providing a reference and basis for the design of more complex electronic systems in the future.