Application of portable amplitude-frequency characteristic tester based on 51 core and FPGA device

In modern power electronic systems, with the increase in the workload of field testing and field maintenance, new requirements have been put forward for the current general test instruments. The development of low-cost, small-volume portable amplitude-frequency characteristic testers has far-reaching practical significance. At present, there are three main technical approaches to the development of amplitude-frequency characteristic testers in combination with new microprocessor chips: (1) Using a single-chip microcomputer as the main control chip and realizing some hardware functions through software programming. This solution can effectively reduce the complexity of the system, but the real-time performance is not satisfactory. (2) Using programmable logic devices (such as FPGA) for design can effectively solve the real-time processing problem of high-speed data streams, but it has great difficulties in the design of human-computer interfaces. (3) Using a combination of single-chip microcomputers and FPGA chips, through the design of external bus connections and data transmission protocols, the system has the advantages of both, thus becoming the mainstream solution preferred by designers.

The development of modern EDA (Electronic Design Automation) technology and the introduction of large-scale FPGA devices make it possible to design embedded 8051 IP cores in single-chip FPGA chips. By applying modern EDA technology, taking FPGA devices as the hardware platform and using VHDL language programming, a microcontroller chip IP (Intellectual Property) core that is fully compatible with the MCS-51 series single-chip microcomputer instruction system can be realized. Based on this, this paper proposes a new approach to the design of an amplitude-frequency characteristic tester. The system uses FPGA as the core acquisition and processing module, and the embedded MC8051 core (hereinafter referred to as the 51 core) developed by Oregano as the display control core. The system generates the sweep signal source required by the system through the idea of ​​the sine lookup table IP core plus the D/A module inside the FPGA. At the same time, a 2.4-inch TFT color screen LCD display is used for human-machine interface design, realizing the basic functions of a portable amplitude-frequency characteristic tester. The instrument has the advantages of miniaturization, wide bandwidth, simple operation, high measurement accuracy, and friendly interface display, and has a broad application space.

1 System composition and working principle

1.1 System composition

The system mainly consists of a sinusoidal excitation signal generation module and a signal acquisition, processing and real-time display module. The former uses the idea of ​​"IP core + high-speed D/A" to generate a frequency sweep signal, and the latter mainly includes an FPGA core board, a dual-channel high-speed A/D and a human-computer interaction interface. Driven by the system clock and trigger signal, the output signal of the network to be tested and the excitation signal of the system are collected at the same time, and corresponding data processing is performed to realize the amplitude-frequency characteristic test of the active or passive four-terminal network. The system composition block diagram is shown in Figure 1.

The core issues that need to be solved in system design are: (1) The initialization configuration of the 51 core. The 51 core used by the system can be directly connected to the internally defined signals of the FPGA through the port instantiation of the top-level file, while the memory module used by the 51 core requires the user to configure it. (2) The rate matching problem of the data stream. The data rate obtained by A/D acquisition far exceeds the computing and processing capabilities of the 51 core, so the data cache module must be designed in the system. (3) The display control of the color LCD. The display part is the key module of the instrument. The system uses TFT-LCD display technology, which can be used for a friendly human-machine interface design. However, the initialization timing of the color LCD is extremely complex, and the real-time display of dynamic curves and measurement data must be optimized. These problems have been reasonably solved in the actual design.

1.2 Measurement principle

For a linear time-invariant (LTI) system, the impulse response is h(t). When the excitation is a sinusoidal signal e(t) = Acos(?Brown0t+?Z), the zero-state response of the system is:

From this we can see that the steady-state response of the system output is also a sinusoidal signal. Its frequency is the same as that of the input signal, but the amplitude and phase have changed. The amplitude becomes |H(j?Brown0)| times the amplitude of the original excitation signal. |H(j?Brown0)| is called the amplitude-frequency characteristic of the circuit network.

When the system is working, a sinusoidal frequency sweep signal with equal amplitude is used as the input signal to stimulate the network under test. The starting frequency, ending frequency, frequency step value and sweep time of the frequency sweep signal can be set by key input, or the system default setting method (sweep range 1 kHz~1 MHz, frequency step 1 kHz, sweep time 1 s) can be used. The high-speed A/D collects the output signal and the original excitation signal of the network, and obtains the envelope data of the network output signal through the peak detection program in the FPGA, and calculates the gain data of different frequency points by comparing with the amplitude of the excitation signal. An asynchronous FIFO is used as a buffer for transmitting data between the FPGA and the 51 core, and it is configured as a "ping-pong" working mode. When the trigger signal arrives, the gain data is written into the asynchronous FIFO in a certain format and rate. After a certain amount of data is stored in the FIFO, the data is read out and sent to the LCD module under the control of the synchronous clock of the 51 core, and the data is prohibited from being written into the FIFO to realize the display of the amplitude-frequency characteristic curve.

2 System Hardware Design

The system hardware mainly realizes the functions of generating sine frequency sweep signal, collecting and processing network output signal, transmitting data and TFT liquid crystal module interface circuit. The overall hardware block diagram is shown in Figure 2.

2.1 FPGA core board module

The FPGA core board module is the core of the system. The FPGA minimum system board and related A/D and D/A circuits are designed according to the needs. Among them, the FPGA minimum system board uses the XC3S400-PQ208 400,000-gate chip of the Spartan3 series of Xilinx. The core board uses 5 V input, and three AMS1117s are used to realize the level conversion from 5 V to 3.3 V, 5 V to 2.5 V and 5 V to 1.2 V. A 40 MHz active crystal oscillator is used on the board to meet the high-speed design requirements. The A/D is the high-speed analog/digital conversion chip AD9224 of ADI Company, which has 12-bit accuracy and low power consumption. The D/A uses the high-performance and high-speed AD9764AR chip, which has 14-bit resolution and excellent dynamic noise-free distortion range.

2.2 Design of frequency sweep signal source

The performance indicators of the frequency sweep signal source directly affect the test accuracy of the instrument. This article uses DDS technology to generate frequency sweep signals. There are two ways to choose from. One is to use a dedicated DDS chip, such as AD9854, to use FPGA to send frequency control words to generate frequency sweep signals; the other is to use the sine lookup table IP core integrated in the FPGA. This is a method of using "IP core + D/A" to implement DDS technology. On the premise of fully improving the utilization of FPGA internal resources, it can effectively reduce the hardware complexity and cost of the system. Therefore, the system adopts this method.

The design environment uses Xilinx's ISE7.1, and the sine lookup table IP Core is generated through the Core Generator. The waveform data in the lookup table is stored in the block memory of the FPGA. The relationship between the input phase control word THETA of the lookup table IP core and the actual phase is:

The frequency accuracy fully meets the design requirements.

2.3 System Interface Module

The 51 core has an 8-bit bus width and realizes the interface connection with the FPGA module through internal port mapping. In order to realize the real-time transmission and display of FPGA collected data, in addition to the data bus (data), the interface design also requires an address bus (addr) and a control bus (w/r_en). According to the communication protocol set by the program, the data cached in the FIFO is communicated to realize data transmission and decoding display. The connection method of the system interface module is shown in Figure 3.

3 System Software Design

The system software design mainly completes the initialization of the sine lookup table IP core, the design of the peak detection program, the design of the asynchronous FIFO, the design of the communication protocol between the FPGA and the asynchronous FIFO, and the synchronous display. The overall block diagram of the software design is shown in Figure 4.

3.1 Initialization configuration of 51 kernel

The 51 core adopts a fully synchronous design scheme, which controls the read and write operations of each storage unit under a unified clock signal. According to the processing speed requirements of the 51 core, a 20 MHz clock is used in the design, and the clock signal is obtained by dividing the system total clock. In the design, the C language code is first compiled in the Keil programming environment. The code is mainly responsible for the initialization of the LCD and the decoding and display of the real-time data collected by the FPGA. The .hex file generated after compilation is converted to the corresponding format to generate a .coe file type that can be loaded by the ROM resources of the FPGA.