Actual combat: Strange problems encountered in ADC testing?

Figure 1. Normal and abnormal FFT results for AD9684 ADC sampling at 500 MSPS, 170.3 MHz, AIN = –1 dBFS.

According to the customer's report, these FFT results not only look strange, but also inconsistent. This state also fits my initial guess about the problem: the converter's input sampling clock receiver oscillates on its own because the clock source is turned off or not connected. This state may also occur if the cable connecting the clock is discontinuous or the components in the signal path are not reliable. As I said, this problem was quickly solved because I have seen similar results many times. You may also see other FFT results under this working condition, as shown in Figure 2:

Figure 2. Sampled FFT results of unstable clock oscillation.

In almost all applications, you will want the sampling clock input to be a single frequency signal. Looking in the frequency domain, you will see that any variations due to phase or thermal noise, frequency instability, or unwanted frequency content will cause the expected relationship between the sampling clock and the analog input signal to deviate from it.

What is the culprit for this? The sampling clock inputs to high speed ADCs are usually differential inputs with the same common-mode bias, and the receivers have very high gain. Therefore, without a differential signal applied, the inputs are all biased at the same voltage, and any non-common-mode noise will cause the sampling clock receiver to oscillate. In this case, the resulting oscillation will not be a single frequency (if it were, it would be a more desirable characteristic). The frequency will vary randomly. When the sampling clock frequency varies randomly, the energy of the analog input will be distributed in the Nyquist bandwidth frequency domain.

In most cases, you can simply recognize this, restore the expected clock reference signal, and continue testing. However, if you want to verify this issue, observe the data clock output (DCO) of the ADC (note that this method does not apply to the output of JESD204B). This signal is usually a delayed version of the ADC sampling clock, or a divided version of the sampling clock (if you use any digital features that can decimate the data rate). For the normal and abnormal FFT results in Figure 1, the corresponding data clock output is shown in Figure 3.

Figure 3. The ADC data clock output for the two FFT cases shown in Figure 1.

You can see that the period is variable, which is what we expect. Of course, I understand why you might not recognize this the first time (or even the first few times) you encounter this problem. Because the test bench appears to be working properly based on the panel values, but the test results are suddenly confused. Is the ADC broken? Is the data acquisition confused? Is the software corrupted? None of them, it's just that there is a signal source missing.