10 RISC-V Companies to Watch

Source: This article is translated from "Designnews" by the public account Semiconductor Industry Observer (ID: icbank), thank you.

Because of its unique open source characteristics, the chip design open source architecture RISC-V (pronounced "risk five") has become famous in the past few years.

The RISC-V ecosystem and companies are springing up like mushrooms. This is partly due to the efforts of the RISC-V Foundation . It is also partly due to startups and established chip and hardware companies that are committed to exploring the potential of open source chip hardware and using it for a variety of applications.

So who are the current leaders in RISC-V, and who will be the future leaders of RISC-V? Therefore, we have collected a list of ten companies developing RISC-V technology.

(Image source: Andes Technology)

Taiwan-based Andes Technology was founded in 2005 as a CPU supplier and is one of the oldest companies currently working in the RISC-V ecosystem. It participated in RISC-V in 2015. In March 2019, the company announced the launch of the 32-bit A25MP and 64-bit AX25MP (block diagram shown above), both of which are RISC-V processors. The company hopes to provide multi-core RISC-V processors to enable advanced applications such as artificial intelligence and advanced driver assistance systems (ADAS).

Both the A25MP and AX25MP support up to four CPU cores; provide efficient cache coherence between private L1 caches; include an optional shared L2 cache; and support I/O coherence for bus masters without caches. They also run at over 1 GHz in a 28nm process and support Linux symmetric multiprocessing (SMP).

Andres said its new RISC-V processors are designed to meet the digital signal processing needs of applications such as image classification, speech recognition and facial detection.

(Image source: Antmicro)

Swedish embedded technology company Antmicro has created Renode , an open source testing and development framework that lets RISC-V developers simulate physical hardware systems, including processors, peripherals, sensors, external environment, and wired and wireless connections .

Renode aims to promote the practical application of RISC-V and help engineers overcome the challenges they encounter when building RISC-V based systems, allowing engineers to quickly explore different architectures, using an open source ecosystem of building blocks and structures provided by Antmicro and the wider developer community.

(Image source: Dover Microsystems)

Massachusetts-based Dover Microsystems is “the first company to deliver true security, privacy, and safety enforcement in silicon.” The company developed CoreGuard (block diagram shown above), a cybersecurity and safety solution for RISC-V processors. Open source brings with it some security concerns, and Dover is one of the few companies that can implement security features into RISC-V processors.

CoreGuard can be implemented in any RISC-V processor, allowing embedded processors to defend against cyberattacks in real time, including flawed security software and security violations. It does this by using hardware interlocks that control the communication between the processor and the rest of the system. CoreGuard has a built-in "micro policy" that tells the processor the difference between good and bad instructions. CoreGuard checks the validity of the communication between the processor and the rest of the system before allowing execution.

“It’s no secret that the same attack on cybersecurity that hit the pandemic is no guarantee for the security of our connected devices and systems,” said Jothy Rosenberg, CEO and founder of Dover, in a December 2018 press statement. “Over the past 18 months, the industry has recognized that preventing attackers from taking over the processor in the first place is where IoT security must begin. By integrating CoreGuard into the processors of embedded systems, organizations in automotive, medical devices, and other related industries can truly ensure they have the safety, security, and privacy they need to build a foundation of trust in the IoT.”

(Image source: Hex Five)

Hex Five created MultiZone Security, which is being called the first trusted execution environment for RISC-V. MultiZone requires no additional hardware, specialized cores, or programming models, and allows for policy-based, hardware-enforced separation of an unlimited number of security domains with full control over data, code, interrupts, and peripherals. Because it is open source, like RISC-V, engineers can also implement open source libraries, third-party binaries, and even old legacy code in MultiZone. Hex Five also maintains an open source repository for MultiZone on GitHub .

In February 2019, Hex Five released the industry’s first secure Internet of Things (IoT) stack for RISC-V as part of a collaboration with cryptography company wolfSSL. The stack is designed to be implemented with FreeRTOS and address the security risks inherent in embedded operating systems.

MultiZone allows engineers to isolate firmware into an unlimited number of independent zones, essentially isolating them in terms of security. The result, according to Hex Five, is to prevent shared memory attacks and other exploits from propagating throughout the system. Any vulnerability is confined to the zone where it occurred.

(Image source: Imperas)

Headquartered in the United Kingdom, Imperas is a virtual software simulation company that has expanded its business to RISC-V. In November 2018, the company released riscvOVPsim, a free RISC-V instruction set simulator that allows engineers to model and simulate single-core RISC-V CPUs. The simulator is aimed at hardware and software engineers and can serve as an entry point to kickstart software development without the need for hardware at hand and hardware-side build and consistency testing. According to Imperas, riscvOVPsim can execute more than 1 billion instructions per second on a standard Windows or Linux PC. It also has configurable runtime settings for all RISC-V specification options to facilitate comparison of runtime results with RTL implementations.

riscvOVPsim is free and available on GitHub for download, along with the latest RISC-V conformance test suite and framework . It includes Imperas' free use license, supporting both commercial and academic use. The open source model is licensed under the Apache 2.0 license.

(Image source: Microsemi)

Microsemi is a subsidiary of Microchip Technology and a producer of RISC-V CPUs and FPGAs. The company's Mi-V RISC-V core is available in its PolarFire family of RISC-V-based SoCs. The PolarFire SoC is designed to provide a low-power, flexible solution for embedded engineers who want to develop FPGA-based IoT devices. The company also offers a full suite of software products for its RISC-V hardware for developing, compiling, and debugging embedded firmware.

(Image source: SiFive)

SiFive, a San Francisco-based startup, was the original RISC-V company and the one that put RISC-V on the map . Starting in 2015, the company released a number of RISC-V-based processor cores, targeting development at all levels from enthusiasts to major manufacturers. In 2017, the company released the U54-MC Coreplex (block diagram shown above), the first RISC-V-based chip to support Linux, Unix, and FreeBSD.

This year, the company expanded its portfolio with the launch of the S2 Core IP series of 64-bit microcontrollers for embedded architectures. SiFive said its S2 series is aimed at handling the processing needs of an increasing number of connected devices, handling real-time workloads, and leveraging artificial intelligence and machine learning to varying degrees.

(Image source: Western Digital)

It might be surprising to see a company known for digital storage on this list. But Western Digital has gone all-in on RISC-V, and in 2017 the company pledged to convert all of the more than 1 billion processor cores it ships each year to RISC-V cores. The move is part of Western Digital's desire to move from being considered no longer a storage company to being a data company.

Western Digital has released the SweRV core, which it says will be used in an increasing number of products over the next few years. SweRV is a 32-bit, bidirectional superscalar, nine-stage pipeline core built on 28mm CMOS process technology with clock speeds up to 1.8 Ghz. As of January 2019, Western Digital fully open-sourced the SweRV core and released an instruction set simulator (ISS) that provides comprehensive testing support for SweRV and other RISC-V cores. The company's full open-source library around SweRV is available on GitHub .

Nuclei System Technology is the first RISC-V processor core IP company in China focusing on IoT and edge computing. It is a silver member of the RISC-V Foundation and the vice chairman unit of the China RISC-V Alliance.

The company's founder, Hu Zhenbo, is one of the technical leaders of the domestic RISC-V community. He is the developer of China's first open source RISC-V processor core, the Hummingbird E203, and the author of the first Chinese RISC-V processor design book, "Hand-in-hand Teaching You to Design CPU - RISC-V Processor".

The team has currently launched the CoreLai N200 series of commercial processor cores for deep embedded and low power consumption fields and the first RISC-V open source processor core in China, the Hummingbird E203. Among them, the E203 has become China's first and the world's smallest general-purpose 32-bit RISC-V processor core recognized by domestic and foreign open source communities. After FPGA and ASIC testing and verification, the area and power consumption are better than the ARM processor core of the same level (42.8% of the area of ​​ARM Cortex-M3 after synthesis without ITCM and DTCM), and the performance is improved by about 40%.

The team will expand the product line to provide customers with more RISC-V-based solutions, significantly reduce the cost of using domestic processor cores, accelerate the response speed of processor core demand in the local Internet of Things (IoT) and edge computing fields, and empower China's chip industry.

GreenWaves Technologies was founded in 2014 and is headquartered in Grenoble, France. It is a fabless semiconductor startup and one of the earliest chip suppliers in the RISC-V open source ecosystem. It is committed to designing ultra-low power disruptive embedded solutions for AI computing of images, sounds and vibrations in sensor devices, and transforming the market of smart sensors and IoT terminal devices.

In February 2018, the company finally successfully released its first-generation product GAP8, which was manufactured using the 55nm ultra-low power process.

As the world's first IoT application processor, GAP8 is designed with eight plus one RISC-V-based high-efficiency cores and embedded extended instruction sets, which gives it an extremely energy-efficient architecture. Secondly, its hardware convolution acceleration engine can speed up neural convolution calculations by three times and save energy by five times. In addition, it integrates power management and other functions. GreenWaves has set six working modes for the entire SoC, so that the voltage and frequency can be dynamically adjusted accordingly, and the power consumption is only the power consumption required for any given task. It is revealed that in deep sleep, the power consumption is only 1uA, and even under full load, the power consumption is only about 80mw. This energy efficiency ratio is not available in most processors on the market.

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