Detailed explanation of chip design and production process

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We are all people in the electronics industry. We know a lot about chips and various packages, but do you know how a chip is designed? Do you know how the designed chip is produced? After reading this article, you will have a general understanding.

Complex and tedious chip design process

The chip manufacturing process is like building a house with Lego. First, there is a wafer as the foundation, and then after the chip manufacturing process is stacked up layer by layer, the necessary IC chips can be produced (these will be introduced later). However, without a blueprint, no matter how strong the manufacturing capabilities are, it is useless. Therefore, the role of the architect is very important. But who is the architect in IC design? This article will introduce IC design.

In the IC production process, ICs are mostly planned and designed by professional IC design companies. Well-known manufacturers such as MediaTek, Qualcomm, and Intel all design their own IC chips and provide chips of different specifications and performances for downstream manufacturers to choose from. Because ICs are designed by each manufacturer, IC design relies heavily on the skills of engineers, and the quality of engineers affects the value of a company. However, what steps do engineers take when designing an IC chip? The design process can be simply divided into the following.

The first step of design is to set goals .

The most important step in IC design is specification formulation. This step is like deciding how many rooms and bathrooms you need before designing a building, and what building regulations you need to comply with. After all the functions are determined, you can design it so that you don’t have to spend extra time on subsequent modifications. IC design also needs to go through similar steps to ensure that the designed chip will not have any errors.

The first step in specification formulation is to determine the purpose and performance of the IC and set the general direction. The next step is to check which protocols must be met. For example, the chip of a wireless network card must comply with IEEE 802.11 and other specifications. Otherwise, the chip will not be compatible with products on the market and cannot be connected to other devices. The last step is to determine the implementation method of the IC, allocate different functions into different units, and determine the method of connecting different units. This completes the specification formulation.

After designing the specifications, the next step is to design the details of the chip. This step is like taking a preliminary note of the building plan, outlining the overall outline to facilitate subsequent drawing. In IC chips, the circuit is described using hardware description language (HDL). Commonly used HDLs include Verilog, VHDL, etc., which can easily express the function of an IC through program code. The next step is to check the correctness of the program function and continue to modify it until it meets the expected function.

▲ Verilog example of a 32-bit adder.

With computers, everything becomes easy

After the complete plan is drawn, the next step is to draw a flat design blueprint. In IC design, the logic synthesis step is to put the correct HDL code into the electronic design automation tool (EDA tool) and let the computer convert the HDL code into a logic circuit to generate the following circuit diagram. After that, repeatedly confirm whether the logic gate design meets the specifications and modify it until the function is correct.

▲ The result of the control unit after synthesis.

Finally, the synthesized code is put into another EDA tool for circuit layout and routing. After continuous testing, the following circuit diagram will be formed. In the figure, you can see different colors such as blue, red, green, and yellow. Each different color represents a mask. As for how to use the mask?

▲ The commonly used calculation chip - FFT chip, completes the result of circuit layout and routing.

Layer upon layer of masks, stacking up a chip

First of all, it is known that an IC will produce multiple masks. These masks have upper and lower layers, and each layer has its own task. The figure below is a simple mask example, taking the most basic component in integrated circuits, CMOS, as an example. The full name of CMOS is complementary metal-oxide-semiconductor, which is a combination of NMOS and PMOS to form CMOS. As for what is metal oxide semiconductor (MOS)? This component widely used in chips is difficult to explain, and it is also difficult for ordinary readers to understand, so I will not go into details here.

In the following figure, the left side is the circuit diagram formed after the circuit layout and winding. We have already known that each color represents a mask. The right side shows the appearance of each mask being spread out. The production starts from the bottom layer, following the method mentioned in the previous article on the manufacture of IC chips, and is produced layer by layer, and finally the desired chip will be produced.

At this point, you should have a preliminary understanding of IC design. It is clear that IC design is a very complex profession. Thanks to the maturity of computer-aided software, IC design has been accelerated. IC design factories rely heavily on the wisdom of engineers. Each step described here has its own specialized knowledge, which can be independently developed into multiple professional courses. For example, writing hardware description language does not simply require familiarity with programming languages, but also requires understanding how logic circuits work, how to convert the required algorithms into programs, and how synthesis software converts programs into logic gates.

What is a wafer?

In semiconductor news, wafer fabs are often mentioned in terms of size, such as 8-inch or 12-inch wafer fabs. However, what exactly is a wafer? What does the 8-inch part refer to? And what are the difficulties in producing large-sized wafers? The following will gradually introduce the most important foundation of semiconductors - what exactly is a "wafer".

Wafer is the basis for manufacturing various computer chips. We can compare chip manufacturing to building a house with Lego blocks, by stacking layer by layer, to complete the desired shape (that is, various chips). However, if there is no good foundation, the house will be crooked and not what you want. In order to make a perfect house, a stable substrate is needed. For chip manufacturing, this substrate is the wafer described next.

(Souse: Flickr/Jonathan Stewart CC BY 2.0)

First, let’s recall that when we were playing with Lego blocks as children, there was a small round protrusion on the surface of the blocks. With this structure, we can stack two blocks firmly together without using glue. Chip manufacturing is also similar to this method, fixing the atoms and substrates added later together. Therefore, we need to find a substrate with a neat surface to meet the conditions required for subsequent manufacturing.

Among solid materials, there is a special crystal structure - single crystal. It has the characteristic that atoms are closely arranged one after another, forming a flat atomic surface. Therefore, using single crystal to make wafers can meet the above requirements. However, how to produce such a material? There are two main steps, namely purification and crystal pulling, after which such a material can be completed.

How to manufacture single crystal wafers

Purification is divided into two stages. The first step is metallurgical purification. This process mainly involves adding carbon to convert silicon oxide into silicon with a purity of more than 98% by oxidation-reduction. Most metal refining, such as iron or copper, uses this method to obtain metals of sufficient purity. However, 98% is still not enough for chip manufacturing and still needs to be further improved. Therefore, the Siemens process will be further used for purification, so that high-purity polysilicon required for semiconductor processes can be obtained.

▲ Silicon column manufacturing process (Source: Wikipedia)

Next comes the crystal pulling step. First, melt the high-purity polysilicon obtained earlier to form liquid silicon. After that, contact the single crystal silicon seed with the liquid surface and slowly pull it up while rotating. As for why single crystal silicon seeds are needed, it is because the arrangement of silicon atoms is like people queuing, and the front row needs to let the later people know how to arrange themselves correctly. The silicon seed is an important front row, so that the later atoms know how to line up. Finally, after the silicon atoms that leave the liquid surface solidify, the neatly arranged single crystal silicon column is completed.

▲ Single crystal silicon column (Souse: Wikipedia)

However, what do 8 inches and 12 inches represent? It refers to the diameter of the crystal column we produce, which looks like the part of the pencil shaft, after the surface is processed and cut into thin discs. As for the difficulty of manufacturing large-size wafers, what is the difficulty? As mentioned earlier, the process of making crystal columns is like making cotton candy, which is formed while rotating. If you have made cotton candy, you should know that it is quite difficult to make large and solid cotton candy, and the process of crystal pulling is the same. The speed of rotation and pulling and the control of temperature will affect the quality of the crystal column. Therefore, the larger the size, the higher the requirements for speed and temperature of crystal pulling. Therefore, it is more difficult to make high-quality 12-inch wafers than 8-inch wafers.

However, a whole silicon column cannot be made into a substrate for chip manufacturing. In order to produce silicon wafers one by one, the silicon column needs to be cut horizontally into discs with a diamond knife. The discs are then polished to form the silicon wafers required for chip manufacturing. After so many steps, the manufacturing of the chip substrate is completed. The next step is the step of stacking the house, that is, chip manufacturing. As for how to make a chip?

Chips built layer by layer

After introducing what silicon wafers are, we also know that manufacturing IC chips is like building a house with Lego blocks, by stacking layer by layer, creating the shape you want. However, building a house has quite a few steps, and the same is true for IC manufacturing. What are the steps in manufacturing ICs? This article will introduce the process of IC chip manufacturing.

Before we begin, we need to first understand what an IC chip is. IC, the full name of which is Integrated Circuit, is a combination of designed circuits in a stacked manner. By this method, we can reduce the area required to connect the circuits. The following figure is a 3D diagram of an IC circuit. From the figure, we can see that its structure is like the beams and columns of a house, stacked layer by layer, which is why IC manufacturing is compared to building a house.

▲ 3D cross-section of an IC chip. (Source: Wikipedia)

From the 3D cross-section of the IC chip in the above picture, the dark blue part at the bottom is the wafer introduced in the previous article. From this picture, we can more clearly know how important the role of the wafer substrate is in the chip. As for the red and khaki parts, they are the parts that need to be completed during IC production.

First, the red part here can be compared to the lobby of the first floor of a high-rise building. The lobby of the first floor is the gateway of a house. People enter and exit from here. It usually has more functions under the control of traffic. Therefore, compared with other floors, it is more complicated to build and requires more steps. In the IC circuit, this lobby is the logic gate layer, which is the most important part of the entire IC. By combining multiple logic gates together, a fully functional IC chip is completed.

The yellow part is like a normal floor. Compared with the first floor, it is not too complicated, and each floor will not change much when it is built. The purpose of this layer is to connect the logic gates in the red part together. The reason why so many layers are needed is that there are too many lines to be connected together. When a single layer cannot accommodate all the lines, multiple layers are stacked to achieve this goal. Among them, the lines of different layers will be connected up and down to meet the wiring needs.

Layered construction, layer-by-layer architecture

Now that we know the structure of IC, we will introduce how to make it. Imagine if we want to make a detailed drawing with a paint spray can, we need to cut out a masking plate of the pattern first and cover it on the paper. Then spray the paint evenly on the paper, wait for the paint to dry, and then remove the masking plate. After repeating this step, a neat and complex pattern can be completed. Manufacturing IC is similar to stacking layers by masking.

When making IC, it can be simply divided into the above 4 steps. Although the actual manufacturing process will be different, the materials used are also different, but generally the same principle is adopted. This process is slightly different from painting with paint. IC manufacturing is to apply paint first and then cover, while painting with paint is to cover first and then paint. The following will introduce each process.

Metal sputtering: The metal material to be used is evenly sprinkled on the wafer to form a thin film.

Photoresist coating: First, place the photoresist material on the wafer, and then shine a light beam on the unwanted part through the mask (the principle of the mask will be explained next time) to destroy the structure of the photoresist material. Then, use chemical agents to wash away the damaged material.

Etching technology: The silicon wafer without photoresist protection is etched with an ion beam.

Photoresist removal: Use photoresist remover to dissolve the remaining photoresist, thus completing the process.

Finally, many IC chips will be completed on a whole wafer. Then, just cut the completed square IC chips and send them to the packaging factory for packaging. As for what the packaging factory is, we will explain it later.

▲ Comparison of wafers of various sizes. (Source: Wikipedia)

What is nanoprocessing?

Samsung and TSMC are competing fiercely in advanced semiconductor processes. Both want to seize the initiative in foundry business and win orders. It has almost become a battle between 14nm and 16nm. But what do these two numbers mean? What do they refer to? And what benefits and problems will the process shrink bring in the future? Below we will give a brief explanation of the nanometer process.

How small are nanometers?

Before we begin, we need to understand what nanometers actually mean. Mathematically, a nanometer is 0.000000001 meters, but this is a pretty poor example because we can only see a lot of zeros after the decimal point, but we don't have a real sense of it. If we compare it to the thickness of a fingernail, it might be more obvious.

If we actually measure it with a ruler, we can find out that the thickness of a nail is about 0.0001 meter (0.1 mm). In other words, if we try to cut the side of a nail into 100,000 lines, each line is approximately equivalent to 1 nanometer. From this, we can roughly imagine how small 1 nanometer is.

After knowing how small a nanometer is, we also need to understand the purpose of shrinking the process. The main purpose of shrinking transistors is to cram more transistors into a smaller chip so that the chip will not become larger due to technological advancement; secondly, it can increase the computing efficiency of the processor; thirdly, reducing the size can also reduce power consumption; finally, after the chip size is reduced, it is easier to fit into mobile devices to meet the future demand for thinness and lightness.

Let's go back to explore what nano-processing is. Take 14 nanometers as an example. Its process means that in the chip, the smallest line can be 14 nanometers in size. The following figure shows the appearance of a traditional transistor, which is used as an example. The main purpose of shrinking transistors is to reduce power consumption, but which part should be shrunk to achieve this goal? The L in the lower left figure is the part we want to shrink. By reducing the gate length, the current can use a shorter path from the drain end to the source end (if you are interested, you can use Google to search for MOSFET, there will be a more detailed explanation).

(Source: www.slideshare.net)

In addition, computers operate with 0 and 1. How can transistors be used to achieve this purpose? The method is to determine whether there is current flowing through the transistor. When voltage is supplied at the Gate end (green block), current will flow from the Drain end to the Source end. If there is no voltage supply, current will not flow, so 1 and 0 can be represented. (As for why 0 and 1 are used for judgment, if you are interested, you can check the Boolean algebra. We use this method to make computers)

There are physical limits to size reduction

However, the manufacturing process cannot be reduced indefinitely. When we reduce the size of transistors to about 20 nanometers, we will encounter problems in quantum physics, which will cause the transistor to leak electricity, offsetting the benefits of reducing L. As a way to improve it, the concept of FinFET (Tri-Gate) is introduced, as shown in the upper right picture. In Intel's previous explanation, we can know that by introducing this technology, leakage caused by physical phenomena can be reduced.

(Source: www.slideshare.net)

More importantly, this method can increase the contact area between the Gate terminal and the lower layer. In the traditional method (upper left picture), the contact surface is only one plane, but after using FinFET (Tri-Gate) technology, the contact surface will become three-dimensional, which can easily increase the contact area. In this way, the Source-Drain terminal can be made smaller while maintaining the same contact area, which is very helpful for reducing the size.

Finally, why do some people say that major manufacturers will face severe challenges in entering the 10-nanometer process? The main reason is that the size of an atom is about 0.1 nanometers. In the case of 10 nanometers, a line has less than 100 atoms, which is quite difficult to manufacture. Moreover, as long as there is a defect in one atom, such as an atom falling out or impurities in the manufacturing process, unknown phenomena will occur, affecting the yield of the product.

If you can't imagine how difficult this is, you can do a small experiment. Arrange 100 small beads on the table into a 10×10 square, cut a piece of paper and cover the beads, then use a small brush to brush off the beads next to it, and finally form a 10×5 rectangle. This way you can understand the difficulties faced by major manufacturers and how difficult it is to achieve this goal.

As Samsung and TSMC will complete the mass production of 14nm and 16nm FinFET in the near future, both want to compete for Apple's next-generation iPhone chip foundry. We will see quite exciting commercial competition and will also get more power-efficient and thinner mobile phones, thanks to the benefits brought by Moore's Law.

Tell you what encapsulation is

After a long process, from design to manufacturing, we finally get an IC chip. However, a chip is very small and thin. If it is not protected from the outside, it will be easily scratched and damaged. In addition, because the chip is small, it will not be easy to place it on the circuit board manually without a larger shell. Therefore, this article will describe the package.

There are two common packages at present. One is the DIP package that is common in electronic toys and looks like a centipede. The other is the BGA package that is common when buying a boxed CPU. As for other packaging methods, there are PGA (Pin Grid Array) used in early CPUs or QFP (Plastic Quad Flat Package), an improved version of DIP. Because there are so many packaging methods, the following will introduce DIP and BGA packaging.

Traditional packaging, timeless

The first thing to introduce is the Dual Inline Package (DIP). From the figure below, you can see that the IC chip using this package looks like a black centipede under the double-row terminals, which is impressive. This packaging method is the earliest IC packaging technology adopted. It has the advantage of low cost and is suitable for small chips that do not need to connect too many wires. However, because most of them are made of plastic, the heat dissipation effect is poor and cannot meet the requirements of current high-speed chips. Therefore, most of the chips using this package are long-lasting chips, such as the OP741 in the figure below, or IC chips that are not so demanding on operating speed and have smaller chips and fewer terminals.

▲ The IC chip on the left is OP741, a common voltage amplifier. The right picture is its cross-section. This package uses gold wires to connect the chip to the metal pins (Leadframe). (Source: Wikipedia on the left, Wikipedia on the right)

As for the Ball Grid Array (BGA) package, it is smaller than DIP and can be easily placed in smaller devices. In addition, because the pins are located under the chip, it can accommodate more metal pins than DIP.

It is quite suitable for chips that require more contacts. However, this packaging method is more expensive and the connection method is more complicated, so it is mostly used in high-priced products.

▲ The left picture shows a chip using BGA packaging. The right picture shows a schematic diagram of BGA using flip chip packaging. (Source: Wikipedia on the left)
With the rise of mobile devices, new technologies have come to the stage

However, using the above packaging methods will consume a considerable amount of space. Current mobile devices, wearable devices, etc. require quite a variety of components. If each component is packaged independently, it will take up a lot of space when combined. Therefore, there are currently two methods that can meet the requirements of reducing the volume, namely SoC (System On Chip) and SiP (System In Packet).

When smartphones first became popular, the term SoC could be found in all major financial magazines. But what exactly is SoC? Simply put, it is to integrate ICs with different functions into one chip. This method can not only reduce the size, but also reduce the distance between different ICs, and improve the computing speed of the chip. As for the production method, it is to put different ICs together during the IC design stage, and then use the design process introduced earlier to make a mask.

However, SoC is not only advantageous. To design an SoC requires considerable technical cooperation. When IC chips are packaged separately, they are protected by external packaging, and the distance between ICs is relatively far, so there is less chance of cross-interference. However, when all ICs are packaged together, it is the beginning of a nightmare. IC design factories need to change from simply designing ICs to understanding and integrating ICs with various functions, which increases the workload of engineers. In addition, many situations may be encountered, such as the high-frequency signal of the communication chip may affect ICs with other functions.

In addition, SoC also needs to obtain IP (intellectual property) authorization from other manufacturers before it can put the components designed by others into SoC. Because making SoC requires obtaining the design details of the entire IC to make a complete mask, this also increases the design cost of SoC. Some people may question why not just design one by themselves? Because designing various ICs requires a lot of knowledge related to the IC, only companies like Apple, which are rich, have the budget to poach top engineers from well-known companies to design a new IC. It is still much more cost-effective to cooperate and authorize than to develop it by yourself.

A compromise solution: SiP emerges

As an alternative, SiP has jumped onto the stage of integrated chips. Unlike SoC, it is to purchase ICs from various companies and package them at the last time, so there is no need for IP licensing, which greatly reduces the design cost. In addition, because they are independent ICs, the degree of interference between each other is greatly reduced.

▲ Apple Watch uses SiP technology to package the entire computer architecture into a chip, which not only meets the expected performance but also reduces the size, allowing the watch to have more space for batteries. (Source: Apple official website)

The most famous product using SiP technology is the Apple Watch. Because the internal space of the Watch is too small, it cannot use traditional technology, and the design cost of SoC is too high, so SiP becomes the first choice. Through SiP technology, not only can the size be reduced, but the distance between each IC can also be shortened, becoming a feasible compromise. The figure below is the structure of the Apple Watch chip, and you can see that quite a lot of ICs are included in it.

▲ The internal configuration diagram of the S1 chip using SiP packaging in the Apple Watch. (Source: chipworks)

After the packaging is completed, it is time to enter the testing phase, in which it is necessary to confirm whether the packaged IC is operating normally. Once it is correct, it can be shipped to the assembly plant to be made into the electronic products we see. At this point, the semiconductor industry has completed the entire production task.

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