Will CMOS process scaling say goodbye in 2014?

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Traditional semiconductor process scaling is expected to end by 2024, according to a white paper by engineers working on a new semiconductor roadmap. Fortunately, new types of components, chip stacks and system innovations are expected to continue to benefit computing performance, power consumption and cost.

A new white paper published by the International Roadmap for Devices and Systems (IRDS) states that “die costs have continued to decline to date due to the simultaneous scaling of multiple pitches, metal pitches, and cell heights. This trend will continue until 2024.”

After 2024, the white paper mentioned that "there is no longer enough space to layout contacts, and as a result of performance degradation caused by contact multi-pitch (CPP) scaling, it is expected that the physical channel length will saturate at 12nm due to the deterioration of electrostatics, and CPP will saturate at 24nm to retain sufficient power density (~11nm) so that component contacts can provide acceptable parasitic effects."

IRDS is an extension of the International Technology Roadmap for Semiconductors (ITRS), first released in 1965. Last May, IEEE took over and renamed it IRDS, expanding it to cover new system-level technologies.

IEEE expects to officially release the first version of IRDS at an event in Washington, D.C. in November. The new white paper marks a transitional phase toward an updated version.

Many white papers in the ITRS era introduced traditional research, such as CMOS scaling, emerging components and yield, etc. Only a few papers introduced some new areas without falling into the old ways, such as system interconnection, and new computing such as quantum and neural systems.

Semiconductor chips will face challenges in physical size limitations starting in 2021 (Source: IRDS)

Of all the white papers, the so-called “More Moore” is the most detailed in the article. It provides a lot of information about the size and materials of logic and memory components and their key components such as interconnects.

For example, the white paper predicts that FinFETs can continue to scale to 2021 for high-performance logic applications; however, after 2019, there will be a shift to gate-all-around (GAA) transistors and possibly vertical nanowire devices, at which point there will be no room for gate length scaling due to fin width scaling limitations.

The white paper also predicts that inserting high-mobility materials (such as germanium) could "increase the drive current by an order of magnitude."

It also predicts that as chipmakers move to horizontal and vertical GAA transistors, "parasitics will become the dominant knob after 2019 as design rules tighten, and parasitics are expected to play a larger role in critical path performance."

Chip stacking and various emerging devices are expected to improve performance and reduce costs for devices beyond CMOS. "The industry must pursue 3D integration paths such as stacking and monolithic 3D (or serial integration) to maintain system performance and increase power while maintaining cost advantages." IEEE Fellow and IRDS President Paolo A. Gargini said: "Our research team is working to identify challenges and propose possible solutions to break through the current limits defined by Moore's Law."

As chips shrink, new materials will be needed to maintain performance and low power consumption. (Source: IRDS)

System innovation is just around the corner...

A preliminary version of the white paper states about new system architectures: “Many groups are proposing remedies to the limitations of Moore’s Law based on new component entities. Representative new components include neuromorphic circuits, qubits, and spintronics. These new components represent a significant expansion of the traditional focus on CMOS and microprocessors… a significant departure from the existing development path.”

To enable this new architecture, the roadmap also includes a new section on application benchmarks, identifying 11 areas worth tracking, covering a broad range of computing methods.

For the interconnect component, the challenges of wired and wireless connectivity are extensively discussed, including "increasing the use of germanium and III-V materials for advanced RF circuits and integrating them on a silicon-based CMOS platform."

Data centers "will require the development of compact, low-cost power photonic components and compact wiring circuits."

The semiconductor development blueprint predicts that different computing methods will flourish in the future (Source: IRDS)**

Finally, it discusses ensuring that the emerging Internet of Things (IoT) will take "new approaches that require coupling software and hardware." Interestingly, in the prediction of CMOS scaling, Intel's recently announced 3D XPoint is also expected to be one of the new generation of storage memories.

"Although details are still scarce, it is speculated that the OTS (on-threshold switching) properties of chalcogenide-based phase-change materials form the core of the selector element."

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