DUV can also achieve 5nm, a "new" approach

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At IEDM 2019, TSMC announced two versions of its 5nm standard cell layout: a 5.5-track DUV patterned version and a 6-track EUV patterned version [1]. While the metal pitch was not explicitly stated, later analysis of 5nm production (i.e., Apple’s A15 Bionic chip) revealed a cell height of 210nm [2]. For the 6-track cell, this means a metal track pitch of 35nm, while for the 5.5-track cell, the pitch is 38nm (Figure 1). This difference in pitch of just 3nm is significant for the patterning approach. As shown below, choosing the 5.5-track cell for DUV patterning makes a lot of sense.

Figure 1. A 210 nm cell height means 5.5 tracks with a track pitch of 38 nm (left), or 6 tracks with a track pitch of 35 nm (left).

Extending 7nm DUV approach to 5nm

The 5.5 track metal pitch is 38 nm, which is the limit of DUV double patterning. Therefore, it is possible to reuse the same approach used in 7 nm, where the 6 track unit metal pitch is 40 nm [3]. This can be as simple as self-aligned double patterning followed by two self-aligned cut blocks, one for each material to be etched (core or gap) (Figure 2). The minimum pitch of the cut blocks (per material) is 76 nm, allowing single patterning.

Figure 2. SADP followed by two self-aligned cut blocks (one for core material and one for gap material). The process sequence from left to right is: (i) SADP (core lithography followed by spacer deposition and etch-back and gap fill; (ii) cut block lithography to expose gap material to be etched; (iii) refill cut block to fill gap material; (iv) cut block lithography to expose core material to be etched; (v) refill cut block to fill core material. After block formation, self-aligned vias can be partially etched (not shown) [4].

SALELE [5] can be used instead of SADP. This will add an extra mask for the gap material, so a total of four mask exposures are required.

Below 38nm Pitch: Breaking the Multi-Patterning Barrier

For the 3nm node, metal track pitch is expected to be below 30nm [6]. Any pitch below 38nm will require the use of more DUV multi-patterning [7]. However, even for EUV, a considerable amount of multi-patterning can be expected, as the minimum pitch for photoelectron diffusion can actually be as low as 40-50nm for typical EUV photoresists [8,9]. Edge sharpness for a 25nm half-pitch 60mJ/cm2 exposure is severely affected by photon shot noise and photoelectron diffusion (Figure 3).

Figure 3. 25 nm half-pitch electron distribution image with incident EUV dose of 60 mJ/cm2 (absorbed 13 mJ/cm2) and 7.5 nm Gaussian blur. Represents the electron spread function given in reference [9]. Using 1 nm pixels, each photoelectron has 4 secondary electrons.

Is 5nm suitable for everyone?

The 5.5 track cell utilizes DUV double patterning technology, providing an easy migration path from 7nm to 5nm. This may be one of the easier ways for Chinese companies to catch up at 5nm, although this is obviously the limit of what they can do.

refer to

[1] G. Yeap et al., IEDM 2019, Figure 5.

[2] https://www.angstromics.com/p/the-truth-of-tsmc-5nm

[3] https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/#google_vignette

[4] F. Chen, Self-aligned block redistribution and expansion to improve multi-patterning productivity, https://www.linkedin.com/pulse/self-aligned-block-redistribution-expansion-improving-frederick-chen-rgnwc/

[5] Y. Drissi et al., Proc. SPIE 10962, 109620V (2019).

[6] https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/

[7] F. Chen, Extension of DUV multipatterning to 3nm, https://semiwiki.com/lithography/336182-extension-of-duv-multipatterning-toward-3nm/, https://www.linkedin.com/pulse/extension-duv-multipatterning-toward-3nm-frederick-chen/

[8] F. Chen, Why NA is not relevant to resolution in EUV lithography, https://www.linkedin.com/pulse/why-na-relevant-resolution-euv-lithography-frederick-chen-ytnoc, https://semiwiki.com/lithography/344672-why-na-is-not-relevant-to-resolution-in-euv-lithography/

[9] T. Kozawa et al., JVST B 25, 2481 (2007).

Reference Links

https://semiwiki.com/lithography/347246-application-specific-lithography-patterning-5nm-5-5-track-metal-by-duv/#comment-43825

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