How will future chips develop?

In 1947, John Bardeen, Walter Brattain, and William Shockley invented the transistor, a small device that transformed the entire electronics industry. By 2022, the advent of the transistor has officially entered its 75th anniversary, which also triggered a lively panel discussion at IEDM 2022. It also sparked debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and the next great memory architecture.

Industry veterans from the memory, logic and research communities cite High-NA EUV production, NAND flash with 1,000 layers and hybrid bonding as drivers. Hybrid bonding will be used to combine different materials in devices as well as stacked complementary FETs (CFETs).

Regarding the expansion of DRAM technology, Seok-Hee Lee, technical advisor of SK Hynix's Solidigm division and former CEO of SK hynix, said: "The next generation of DRAM may adopt a new configuration, that is, a 3D design in which the capacitor stretches laterally." "Yes, a lot of people are working on it now because you can relax the constraints of the capacitor and you can form it in a horizontal direction. But there are still a lot of challenges. However, we think that with hard work in the next five years, you can We'll see some form of 3D DRAM."

Gosia Jurczak, general manager of global emerging memories at Lam Research, agreed with Lee's point of view.

In this panel discussion, Tahir Ghani, senior researcher at Intel; Anton DeVilliers, vice president of R&D and lithography pattern researcher at TEL; Serge Biesemans, senior vice president of semiconductor R&D at imec; David Gundlach, head of NIST's Nanoscale Device Characterization Division; Micron Advanced and Emerging Memory Vice president Nirmal Ramaswamy and IBM researcher Heike Riel both expressed their views on the future of the industry. Below are excerpts from that discussion.

While the industry is continuing to explore new materials, silicon CMOS is likely to remain strong for the foreseeable future. “Silicon channel is as well-established a material system that we have in transistors that it’s actually very hard to beat,” said Lam’s Jurczak. "We shift our focus to 20 years ago, when silicon germanium channels were first announced, which had very clear mobility advantages in long channel transistors. However, we had to wait until 2020 to see silicon germanium in products for the first time aisle.

Another example is III-V materials. Again, we've seen huge advantages in its electron mobility, and it's actually a very good candidate for NMOS transistors as well. However, five years later, researchers published a large number of papers on III-V materials and concluded that in short-channel transistors, these materials do not have any advantages because the electron movement rate decreases and we get high reliability. transsexual.

Despite some limitations, silicon CMOS remains the most understood and mature material. "With this history, when I look at 2D candidates, I'm skeptical about how we're going to do this in the next 10 to 20 years," Jurczak said. "What we're seeing today in mobility is, It's not really at the level we see in silicon," Jurczak added.

Still, there is optimism that stacking 2D materials and mobility may increase. "It's a really good option," said IBM's Riel. “With nanosheets, you see the effect of stacking, and it’s a fundamental advance in gate-all-around. The community is good at identifying challenges and then addressing them. We started using them more than 20 years ago The ring fence, it’s here now.”

“由二维材料制成沟道的设备需要堆叠，”imec 的 Biesemans 说。“很难想象像我们在平面或 finFET 技术中那样并排放置 nMOS-pMOS-nMOS-pMOS-…。二维材料器件应该出现在堆叠的 nMOS 和 pMOS 层中。要创建该路径（path），首先应该使用堆叠硅，然后更换沟道材料。但strain并不存在。我甚至认为strain已经消失了。” 他补充说，随着混合键合工艺的成熟，它们将变得更加商品化，最终允许在晶体管级别实施。

“Stacking will be able to combine materials with different atomic lengths and different substrates compared to non-stacked options,” said Intel’s Ghani.

TEL's DeVilliers notes that stacking and hybrid bonding are far from trivial. "Our friends in the storage world showed us how to stack," he said. "Stacking is not hard. The hard part is making money by stacking. There is a lot to learn about 3D NAND stacking from the tooling side."

Moving from equipment needs to interconnect needs, Jurczak pointed to the need for lower thermal budgets and alternative materials. Panelists discussed the latest trends in rear power supplies. As dimensions approach a few nanometers, interconnecting front-side vias becomes increasingly difficult, especially patterning, covering, and opening all vias.

NIST's Gundlach, meanwhile, talked about the need to maintain metrological precision and accuracy. “Our ability to solve problems better on a larger scale becomes very important,” he said. “While ppm purity [of materials] may be sufficient at one point, perhaps we are moving to ppb, which will require innovation in standard measurement services throughout the supply chain and product lifecycle.”

Micron's Ramaswamy focuses on scalability of DRAM devices. "DRAM scaling consists of several blocks, and we can choose which one has fundamental limitations. Many features are below 10 nanometers, and the contacts are even smaller. We can talk about a few tenths of a nanometer, or a few dopant atoms. But typically Down, DRAM is always about capacitors, aspect ratio is about 50:1 and increasing, dielectric constant is above 40, can we get to 50 without too much leakage, I would say yes. capacitor."

SK Hynix's Lee agrees. "Capacitors are always a challenge with 1T-1C structures with geometric scaling. If you look at dielectric materials, you remember the relationship between conduction band offset and permittivity. You have that relationship. So yes, you can Find a material that's different than zirconia based, but then you have less conduction band shift so leakage current is less of an issue but that's always a change, fundamentally, if I have to choose one. , the capacitor is the limiter.”

IEDM always features papers covering various alternative memory architectures. Caching is a particularly popular area. But experts were asked if any technology could replace entrenched NAND and DRAM devices. "DRAM and NAND are very powerful and hard to beat," Jurczak said. "So the future of DRAM is DRAM, but emerging memories may fill some of the gaps."

The stacking capabilities of hybrid bonding may provide new uses for DRAM.

"With advanced packaging technology, some companies have stacked SRAM on CPUs," Lee said. "But after level 3, can we have level 4, an additional layer of cache? Depending on the workload, you might benefit from that additional layer of cache."

DRAM can meet this need. "There are endurance issues with emerging memories, but not necessarily non-volatile memory, and the industry already has the ability to mass-produce DRAM and connect it using advanced packaging," Lee said.

Intel's Ghani agreed. "This certainly opens up a range of possibilities that weren't available before," he said. "Although off-chip, the advanced packaging enables low off-chip latency and high bandwidth."

Another topic of discussion was the return on investment of moving to near-memory or in-memory computing, specifically shortening the distance between memory and processing. "If we look at mobile computing, on average we lose about 15 percent of mobile data power consumption," said Micron's Ramaswamy. "So for sustainability, energy efficiency is very important. It's a natural process. It's going to happen."

But when is another matter. Ramaswamy noted that architects and programmers need to come together to show how near-memory/in-memory computing will work. He said it will take time to resolve.

EUV lithography is optional at 16/14nm, but is considered essential at 7nm and below. But EUV has lost steam below 5nm, and the leading foundries—Samsung, Intel, TSMC—are looking toward High NA (0.55) EUV and beyond. The big question is what happens next? Is it maskless patterning or some form of self-assembly?

“In 2025, High NA EUV will be in production,” Intel’s Ghani said. “Even in the future with higher NA EUV tools, we may have to adopt pitch doubling or quadruple patterning schemes to achieve continued dimension scaling. But I don’t see a fundamental impediment in the next six to eight years. ”

Metrology looks more like a barrier to advancing to the 1nm node and below, especially as the number of 3D structures increases. "Metrics science has not kept pace with EUV," said NIST's Gundlach. "Can you make measurements in a high-volume environment using EUV, or are we at the limit of not being able to see what we're making? There's a lot of opportunity there."

Self-assembly does not appear to compete with existing patterning methods, and multiple methods can be used together and for different metal layers.

The transition from 200+-layer to 1,000-layer NAND is underway, but it will require new materials, NAND architecture and improved capital equipment to increase throughput.

“We’re at 232 layers now, and we’ll probably get to 1,000 by the end of this decade,” said Micron’s Ramaswamy. “We have a lot of very critical etch, deposition and fill processes. We need a device roadmap to keep up with technology scaling. pace. We don’t have the ability to manufacture 1,000 layers now. All processes need to be cost-effective and have the right tolerances.”

Lee agrees. "We have to grow the stack because you can't keep adding layers," he said. "You also have to scale the celling, and high aspect ratio etching is a big problem. A few years ago, on another forum, I said if you provide a tool that can etch 12 wafers per hour, I have a problem. Is it practical It gets worse. Engineers will find a solution."

How quantum computing will be used in the future is another big unknown.

“Quantum is not meant to replace regular CMOS transistors,” IBM’s Riel said. “That’s not what quantum computing is about. But quantum is here to solve mathematical problems that classical digital computers could never solve. There are many examples, but we almost forget We've learned a lot about them because they work well in some cases, but not so well in other cases, and we find that quantum computing will help solve these problems."

Qubit generation and coherence have been steadily improving. "The first 433-qubit processor was released about three weeks ago, and we had clear goals to improve performance in terms of speed, scale and quality," Riel said. "We know from the silicon industry that you need a clear roadmap, so I'm very optimistic. We're at the beginning of something new, and it's not about replacing the transistor, it's about enhancing it."

For quantum computing, this is a long process. NIST's Gundlach points out that Julius Edgar Lilienfeld conceived of the solid-state amplifier as early as 1925, laying the foundation for quantum devices. “If you think back the Lilienfeld patent was decades ago, so the industry is very good at taking a long-term view and being able to deliver on it.”

Two hot topics in the chip industry are attracting talent and improving sustainability, and the two are intertwined. Panelists agreed that young people care deeply about the health of the planet, so recruitment efforts need to better communicate the environmental impact they can have by working in the global semiconductor sector.

“We are doing an interesting experiment where a large tool company in South Korea has developed a special program to secure employment for college graduates,” SK Hynix’s Lee said, noting that novel approaches are needed. "If you're a professor, you have strong opinions because the mission is more than just getting a job. Sustainability is a huge topic - net zero - and as a semi-manufacturing company, we have a lot to do. About Chemicals and gases, we're still using greenhouse gases and working with material suppliers to replace them. Semiconductor equipment consumes a lot of electricity and we have to use renewable energy to do that, and a company can't do that without working with a lot of different parties. There's no way to do that, and a lot of companies have signed up, so it's going to happen."

Still, it's a huge challenge, especially with some of the chemicals and gases used in fabs. "The question is, 'If we can't replace the gas, can we make the abatement system more efficient? Unfortunately, that usually means more power. We have to optimize the whole system, possibly incorporating abatement and merging pumps," Jurczak said.

Micron's Ramaswamy talked about the three pillars of ESG (environmental, social and governance) around water use, hazardous waste generation and disposal. "We have set very strong targets on sustainability - particularly wastewater recycling, reuse of up to 75 to 90 percent and zero hazardous waste to landfill. Getting fully renewable energy is also a big deal."

In some ways, this is getting easier. "Awareness has been increasing over time, but we need to act in the most effective way," IBM's Riel said. “But some things, like saving energy, can be done right away.

Regarding the semiconductor workforce, Jurczak emphasizes the passion for technology that semiconductors inspire. “When I ask my colleagues why they are still in the industry, the top reason they give is passion.”

Nearly 30% of IEDM attendees were first time attendees. This is where the growth is, and this is where the jobs of the future will be. The chip industry is entering an unprecedented era of innovation and growth, from equipment research and development to new materials and tighter integration. The shift to advanced packaging and all the challenges that come with it will require new levels of collaboration to offset the gradual waning of Moore’s Law and rising chip design and manufacturing costs.

A poll of our audience revealed that talent walls and cost walls are the biggest barriers to continued progress in semiconductors—much higher than the perceived performance, power, and memory walls. But these walls are only temporary, and smart people equipped with a host of new enabling technologies and materials may be able to break down all of them—designing new approaches around them.

*Disclaimer: This article is original by the author. The content of the article is the personal opinion of the author. The reprinting by Semiconductor Industry Watch is only to convey a different point of view. It does not mean that Semiconductor Industry Watch agrees or supports the view. If you have any objections, please contact Semiconductor Industry Watch.

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