[Shishuo Design] Customers complain about excessive power consumption? Teach you how to find the "culprit"

It was an ecstatic moment, I had finally found the problem, and although I didn't scream along the way, it took me a while to get over my excitement and sit down to explain it to him.

A typical CMOS digital input looks like this:

Figure 1. Typical CMOS input circuit (left) and CMOS level logic (right)

When this input is driven at the recommended high (1) or low (0) levels, the PMOS and NMOS FETs turn on one at a time, never at the same time. There is an uncertainty zone in the input drive voltage, called the "threshold region," where both the PMOS and NMOS may be partially turned on at the same time, creating a leakage path between the supply rail and ground. This can happen when the input is floating and encounters stray noise. This explains both the fact that the power dissipation on the customer board is high, and why the high power dissipation occurs randomly.

Figure 2. Both the PMOS and NMOS are partially on, creating a leakage path between power and ground.

In some cases, this can cause a condition like latch-up, where the device continues to draw too much current and eventually burns out. This is arguably easier to find and fix because there is smoke in the device, and that is the smoking gun. The problems my customers report are more difficult to deal with because they are fine when you test them in a cool environment in the lab, but can cause a lot of trouble when you get them into the field.

Now that we know the source of the problem, the obvious solution is to drive all unused inputs to a valid logic level (high or low). However, there are some subtleties to be aware of. Let's look at a few more cases where improper handling of CMOS inputs can cause trouble. We need to broaden the scope and consider not only inputs that are completely disconnected/floating, but also inputs that appear to be connected to appropriate logic levels.

If you simply connect the pin to the supply rail or ground through a resistor, you should be careful about the size of the pull-up or pull-down resistor used. It, along with the source/sink current of the pin, can shift the actual voltage of the pin to an undesired level. In other words, you need to make sure the pull-up or pull-down resistor is strong enough.

If you choose to actively drive the pin, be sure that the drive strength is good enough for the CMOS load you are using. If not, the noise surrounding the circuit may be strong enough to overwhelm the drive signal and force the pin into an unintended state.

A processor that works fine in the lab may inexplicably reboot in the field because noise is coupled into the RESET line that does not have a strong enough pull-up resistor.

Figure 3. Noise coupled into the RESET pin with a weak pull-up resistor can cause the processor to reset.

Figure 4. Noise overdrives a weakly driven CMOS input gate driver, causing a high-voltage bus short.

Figure 6. ADSP-SC58x/ADSP-2158x data sheet quick reference

Figure 5. CMOS inputs rise/fall slowly, causing a temporary short circuit during the transition.

‍ Now that we have discussed some of the problems that can occur with CMOS inputs in a general sense, it is worth noting that some devices are designed to handle these problems better than others. For example, devices with Schmitt trigger inputs are better able to handle signals with high noise or slow edges.

Some of our latest processors are aware of this issue and have taken special precautions in their designs or have published clear guidelines to ensure smooth operation. For example, the ADSP-SC58x/ADSP-2158x datasheet clearly states that some pins have internal termination resistors or other logic circuitry to ensure that these pins do not float.

Finally, as always, it is important to get all the finishing touches right, especially with CMOS digital inputs. ‍