To achieve a high signal-to-noise ratio (SNR), the ADC must have low aperture jitter. ADCs with aperture jitter as low as 60 fs rms are available (AD9445 14-bit 125MSPS and AD9446 16-bit 100MSPS). To avoid degradation of the ADC's performance, a very low jitter sampling clock must be used, since the total jitter is equal to the root sum square of the converter's internal aperture jitter and the external sampling clock jitter. However, the oscillator used to generate the sampling clock is often characterized by phase noise rather than time jitter. The purpose of this article is to present a simple method to convert oscillator phase noise to time jitter.
First, let’s clarify a few definitions. Figure 1 shows a typical output spectrum of a non-ideal oscillator (that is, the presence of jitter in the time domain, which corresponds to phase noise in the frequency domain). The spectrum shows the noise power in a 1 Hz bandwidth as a function of frequency. Phase noise is defined as the ratio of the noise in a 1 Hz bandwidth at a nominal frequency offset, fm, to
the amplitude of the oscillator signal at
frequency
fO
.
[Figure 1: Oscillator power spectrum affected by phase noise]
The sampling process is basically a multiplication of the sampling clock and the analog input signal. This is a multiplication in the time domain, which is equivalent to a convolution in the frequency domain. Therefore, the spectrum of the sampling clock oscillator is convolved with the input and displayed at the FFT output of a pure sine wave input signal (see Figure 2).
[Figure 2:
Effect of sampling clock phase noise on an ideal digitized sine wave]
“Close-in” phase noise “smears” the fundamental signal in multiple frequency bins, reducing the overall spectral resolution. “Wideband” phase noise results in a reduction in the overall SNR, as shown in Equation 1:
Single-sideband phase noise is often used to describe the characteristics of an oscillator, as shown in the phase noise (dBc/Hz) vs. frequency offset fm curve in Figure 3, where the frequency axis is on a logarithmic scale. Note that the actual curve is fitted by multiple regions, each with a slope of 1/f
x
, with x=0 corresponding to the "white" phase noise region (slope = 0dB/10), x=1 corresponding to the "flicker" phase noise region (slope = –20dB/10), and x=2, 3, and 4 regions, which appear in sequence, getting closer and closer to the carrier frequency.
[Figure 3:
Relationship between oscillator phase noise (dBc/Hz) and frequency offset]
Note that the phase noise plot has some similarities to the amplifier's input voltage noise spectral density. Like the amplifier voltage noise, a low 1/f corner frequency is also very desirable for the oscillator.
We have seen that oscillators are often described in terms of phase noise, but in order to relate phase noise to the performance of an ADC, the phase noise must be converted to jitter. To relate this curve to modern ADC applications, an oscillator frequency (sampling frequency) of 100MHz was chosen for ease of discussion, and a typical curve is shown in Figure 4. Note that the phase noise curve is fitted by multiple line segments, with the endpoints of each segment defined by the data points.
[Figure 4:
Calculating jitter based on phase noise]
Converting Phase Noise to Jitter
The first step in calculating the equivalent rms jitter is to obtain the integrated phase noise power over the frequency range of interest, i.e., region A of the curve. The curve is divided into a number of independent regions (A1, A2, A3, A4), each defined by two data points. In general, assuming no filtering between the oscillator and the ADC input, the upper limit of the integration frequency range should be twice the sampling frequency, which is approximately the bandwidth of the ADC sampling clock input.
The selection of the lower limit of the integration frequency range also requires some consideration. In theory, it should be as low as possible in order to obtain the true rms jitter. In practice, however, manufacturers generally do not provide oscillator characteristics when the offset frequency is less than 10Hz, but this can already produce sufficiently accurate results in the calculation. In most cases, if the characteristics at 100Hz are provided, it is reasonable to choose 100Hz as the lower limit of the integration frequency. Otherwise, 1kHz or 10kHz data points can be used.
It should also be considered that "close in" phase noise affects the spectral resolution of the system, while broadband noise affects the overall system signal-to-noise ratio. The most sensible approach is probably to integrate each region separately as described below and examine the magnitude of the jitter contribution in each region. If a crystal oscillator is used, the low frequency contribution may be negligible compared to the broadband contribution. Other types of oscillators may have significant jitter contributions in the low frequency region, and their importance to the overall system frequency resolution must be determined.
Integration of each region yields individual power ratios, which are then summed and converted back to dBc. Once the integrated phase noise power is known, the rms phase jitter can be calculated as follows (in radians, see References 3 to 7 for more information and implications):
Dividing the above result by 2πf
O
converts the jitter in radians to jitter in seconds: Note that there are computer programs and spreadsheets available on the Internet to perform the piecewise integration and calculate the rms jitter, which greatly simplifies the calculation process (References 8, 9).
Figure 5 shows an example calculation that assumes only wideband phase noise is present. The wideband phase noise of –150dBc/Hz was chosen to represent the characteristics of a good signal generator, and the jitter value obtained from this is representative of reality. The phase noise of –150dBc/Hz (expressed as a ratio) is multiplied by the integration bandwidth (200MHz) to obtain an integrated phase noise of –67dBc. Note that this multiplication is equivalent to adding the quantity 10log10[200MHz–0.01MHz] to the phase noise (dBc/Hz). In practice, the lower frequency limit of 0.01MHz can be discarded from the calculation as it does not significantly affect the final result. Using Equation 3, the total rms jitter is approximately 1ps.
[Figure 5:
Example of jitter calculation assuming only broadband phase noise exists]
Crystal oscillators generally have the lowest phase noise and jitter, and several examples are shown in Figure 6 for comparison.
All of the oscillators shown have a 1/f corner frequency of 20kHz, so the phase noise represents a white phase noise level.
The two Wenzel oscillators are fixed-frequency types that provide excellent performance (Reference 9).
It is difficult to achieve such high performance with a variable-frequency signal generator, and a relatively high-quality generator has a performance of –150dBc, as shown.
[Figure 6:
Broadband phase noise floor comparison of 100 MHz oscillators (Characteristics and pricing for the Wenzel ULN and Sprinter series are courtesy of Wenzel Associates)]
It should be noted here that there is a theoretical limit to the noise floor of an oscillator, which is determined by the thermal noise of the matched source:
–174dBm/Hz at +25°C.
Therefore, an oscillator with a phase noise of –174dBc/Hz driving a 50Ω (2.82-Vp-p) load with a +13-dBm output has a noise floor of –174dBc + 13dBm = –161dBm.
This is the case for the Wenzel ULN series shown in Figure 6.
Figure 7 shows the jitter calculations for two Wenzel crystal oscillators.
The data points in each case come directly from the manufacturer’s data sheet.
Due to the low 1/f corner frequency, the majority of the jitter is due to the “white” phase noise region.
The calculated values of 64fs (ULN-Series) and 180fs indicate very low jitter.
The noise contribution of each region is marked for reference.
The total jitter is the root sum of the squares of the individual jitter contributors.
[Figure 7:
Jitter calculation for a low-noise 100MHz crystal oscillator (Phase noise data used with permission from Wenzel Associates)]
In system designs that require low-jitter sampling clocks, the cost of low-noise dedicated crystal oscillators is typically prohibitive.
An alternative is to use a phase-locked loop (PLL) and voltage-controlled oscillator to “clean up” the noisy system clock, as shown in Figure 8.
There are many good references on PLL design (e.g., References 10 to 13), so we will not discuss them further here, except to say that the
lowest phase noise is usually achieved using a narrow-bandwidth loop filter and a voltage-controlled crystal oscillator (VCXO).
As shown in Figure 8, while PLLs reduce the overall phase noise floor, they also tend to reduce the “close-in” phase noise.
Connecting an appropriate bandpass filter after the PLL output can further reduce the white noise floor.
[Figure 8:
Using a phase-locked loop (PLL) and a bandpass filter to condition a noisy clock source]
The effect of including a free-running VCO within the PLL is shown in Figure 9.
Note that the “close-in” phase noise is greatly reduced due to the action of the PLL.
[Figure 9:
Phase noise of a free-running VCO and a VCO connected to a PLL]
ADI offers many different frequency synthesis products, including DDS systems, integer-N and fractional-N PLLs, and more.
For example, the ADF4360 family is a fully integrated PLL with an internal VCO.
The phase noise of the ADF4360-1 2.25-GHz PLL in conjunction with a 10-kHz bandwidth loop filter is shown in Figure 10, and the piecewise approximation and jitter calculations are shown in Figure 11.
Note that even with a non-crystal VCO, the rms jitter is only 1.57 ps.
Figure 10:
Phase noise of the ADF4360-1 2.25-GHz PLL with a 10-kHz bandwidth loop filter.
[Figure 11:
Piecewise approximation of jitter calculation for ADF4360-1 2.25-GHz PLL phase noise]
Historically, PLL design has relied heavily on textbooks and application notes to help design loop filters, etc.
Now, PLL design has become very easy with the free downloadable ADIsimPLL® software from ADI.
To start designing, enter the desired output frequency range to select a circuit, then select the PLL, VCO, and crystal reference.
Once the loop filter configuration is selected, the circuit can be analyzed and optimized in both the frequency and time domains for phase noise, phase margin, gain, spurious levels, lock time, etc.
The program can also calculate rms jitter from the PLL phase noise to evaluate the final PLL output as a sampling clock.
Sampling clock jitter can have a disastrous effect on the signal-to-noise performance of a high performance ADC.
While the relationship between signal-to-noise and jitter is well known, most oscillators are characterized by phase noise.
This article shows how to convert phase noise to jitter so that the degradation in signal-to-noise ratio can be easily calculated.
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Output frequency range: 2050 MHz to 2450 MHz
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2-way frequency output
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3.0 V to 3.6 V power supply
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1.8 V logic compatible
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Integer-N Frequency Synthesizer
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Programmable dual-mode prescaler: 8/9, 16/17, 32/33
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Programmable output power levels
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Three-wire serial interface
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Analog and digital lock detection
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Hardware and software power saving modes
While not as ideal as a costly stand-alone crystal oscillator, a modern PLL using a crystal VCO (and appropriate filtering) can achieve excellent jitter performance suitable for all but the most demanding applications.
With the low jitter requirement, the entire clock distribution problem becomes even more important.
Original article from
Analog Devices
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