Signal and information processing is one of the fastest-growing disciplines in information science in recent years. With the advent of the System On Chip (SOC) era, FPGA is at the forefront of revolutionary digital signal processing. FPGA-based designs can be reprogrammed and debugged in the system, with high throughput, better ability to prevent authorized copying, further reduction of component and development costs, and greatly shortened development time. However, FPGA devices are based on the programming process of SRAM structure. The programming information is immediately lost after power failure. Each time the power is on, the configuration data must be downloaded again, and the device supports multiple configuration methods. Therefore, studying the configuration scheme of FPGA devices is of great value in FPGA system design, which also puts higher requirements on the configuration interface circuit and experimental development equipment used for programming programmable logic devices. Based on the IEEE1149.1 standard and USB2.0 technology, this paper completes the design and implementation of the FPGA configuration interface circuit and experimental development board. Based on a full understanding of the IEEE1149.1 standard and the principles of USB technology, the author tested and analyzed the internal working principle and working timing of the USB-Blaster, a USB data configuration cable specially used by Altcra, and completed the complete software and hardware design and functional timing simulation of the FPGA chip development experimental circuit based on the USB configuration interface. Finally, the author debugged the software and hardware, completed the test and verification, and realized the configuration function of the Altera series PLD and the function of the experimental development board. The USB download interface circuit discussed in this paper has been verified to be directly used in Altera\'s QuartusII development environment, without the need to design communication software on the host side, and its compatibility is improved compared with the existing design. Because PLD (Programmable Logic Device) manufacturers strictly keep their intellectual property rights confidential, the application of configuration circuits based on USB interfaces is greatly restricted, and it also increases the difficulty of developing and designing them by themselves. Compared with the traditional download interface circuit based on PC parallel port, the USB download interface circuit and FPGA experimental development board designed in this paper have higher programming download rate, support hot plug, small size, easy to carry, reduce damage to PC hardware, and have obvious advantages such as SignalTapII embedded logic analyzer and debugging NiosII embedded soft core processor that other download interface circuits do not have. From the perspective of cost, the USB configuration interface circuit and FPGA experimental development board designed in this paper are highly competitive compared with similar products.
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