INDUSTRIAL TEMPERATURE
DDR2 UNBUFFERED SODIMM
VR5DUxxxx18xxx
MODULE CONFIGURATIONS
Viking Part Number
Capacity
512MB
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
4GB
4GB
4GB
4GB
4GB
VR5DU646418EBPyzT
VR5DU646418EBSyzT
VR5DU646418EBWyzT
VR5DU646418EBYyzT
VR5DU646418EBZyzT
VR5DU286418EBPyzT
VR5DU286418EBSyzT
VR5DU286418EBWyzT
VR5DU286418EBYyzT
VR5DU286418EBZyzT
VR5DU286418FBPyzT
VR5DU286418FBSyzT
VR5DU286418FBWyzT
VR5DU286418FBYyzT
VR5DU286418FBZyzT
VR5DU566418GBPyzT
VR5DU566418GBSyzT
VR5DU566418GBWyzT
VR5DU566418GBYyzT
VR5DU566418GBZyzT
VR5DU566418FBPyzT
VR5DU566418FBSyzT
VR5DU566418FBWyzT
VR5DU566418FBYyzT
VR5DU566418FBZyzT
VR5DU126418GBPyzT
VR5DU126418GBSyzT
VR5DU126418GBWyzT
VR5DU126418GBYyzT
VR5DU126418GBZyzT
Module
Configuration
64Mx64
64Mx64
64Mx64
64Mx64
64Mx64
128Mx64
128Mx64
128Mx64
128Mx64
128Mx64
128Mx64
128Mx64
128Mx64
128Mx64
128Mx64
256Mx64
256Mx64
256Mx64
256Mx64
256Mx64
256Mx64
256Mx64
256Mx64
256Mx64
256Mx64
512Mx64
512Mx64
512Mx64
512Mx64
512Mx64
Device
Configuration
64M x 8 (8)
64M x 8 (8)
64M x 8 (8)
64M x 8 (8)
64M x 8 (8)
64M x 8 (16)
64M x 8 (16)
64M x 8 (16)
64M x 8 (16)
64M x 8 (16)
128M x 8 (8)
128M x 8 (8)
128M x 8 (8)
128M x 8 (8)
128M x 8 (8)
256M x 8 (8)
256M x 8 (8)
256M x 8 (8)
256M x 8 (8)
256M x 8 (8)
128M x 8 (16)
128M x 8 (16)
128M x 8 (16)
128M x 8 (16)
128M x 8 (16)
256M x 8 (16)
256M x 8 (16)
256M x 8 (16)
256M x 8 (16)
256M x 8 (16)
Device
Package
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Module
Ranks
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
Performance
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
CAS
Latency
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
CL6 (6-6-6)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
CL6 (6-6-6)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
CL6 (6-6-6)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
CL6 (6-6-6)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
CL6 (6-6-6)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
CL6 (6-6-6)
Notes
Suffix “yz” refers to DRAM vendor and Die revision
Features
200 pin SO-DIMM
Single 1.8V
0.1V Power Supply
Programmable CAS Latency: 3, 4, 5, 6
Burst Length (4, 8)
Burst type (Sequential & Interleave)
Auto & Self-Refresh.
8k/64ms Refresh Period.
Differential CLK (#CLK) inputs.
On-die termination (ODT)
Off-chip driver (OCD) impedance calibration
Serial Presence Detect with EEPROM.
RoHS Compliant* (see last page)
Industrial Temperature (-40C to +95C)
Viking Technology2950
Red Hill Ave
Costa Mesa, CA 92626
Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com
This Data Sheet is subject to change without notice.
Doc. # PS5DUxxxx18xxxyzT
Revision A
Created By: Brian Ouellette
Page 1 of 16
INDUSTRIAL TEMPERATURE
DDR2 UNBUFFERED SODIMM
VR5DUxxxx18xxx
PIN FUNCTION DESCRIPTION
SYMBOL
CK0, CK1
/CK0, /CK1
TYPE
IN
POLARITY
Positive Edge
Negative Edge
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All addresses and control input
signals are sampled on the crossing of the positive edge of CK and negative edge of
/CK. Output data (DQs, DQS and /DQS) is referenced to the crossings of CK and
/CK.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers of the SDRAMs. Taking CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or
ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder
when high. When decoder is disabled, new commands are ignored and previous
operations continue. These input signals also disable all outputs (except CKE and
ODT) of the register(s) on the DIMM when both inputs are high. When both S[0:1] are
high, all register outputs (except CKE, ODT and
Chip select) remain in the previous state.
On-Die Termination control signals
CAS, WE When sampled at the positive rising edge of the clock, /CAS, /RAS, and
/WE define the operation to be executed by the SDRAM.
Reference voltage for SSTL18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Selects which SDRAM bank of four or eight is activated.
During a Bank Activate command cycle, Address defines the row address. During a
Read or Write command cycle, Address defines the column address. In addition to
the column address, AP is used to invoke autoprecharge operation at the end of the
burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2
defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a
Precharge command cycle, AP is used in conjunction with BA0, BA1, and BA2 to
control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are
used to define which bank to precharge.
Data Input/Output pins
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
The optional EVENT pin is reserved for use to flag critical module temperatures and is
used in conjunction with a SPD temperature sensing option.
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A
resistor must be connected from the SDA bus line to VDDSPD on the system planar
to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to VDDSPD on the system planar to act as a pull-
up.
Serial EEPROM positive power supply (wired to a separate power pin at the
connector, which supports from 1.7 Volt to 3.6 Volt (nominal 1.8 Volt, 2.5 Volt and 3.3
Volt) operations.
CKE0 ~ CKE1
IN
Active High
/S0 ~ /S1
IN
Active Low
ODT0 ~ ODT1
/RAS, /CAS,
/WE
VREF
VDD
BA [2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A [14:0]
IN
-
DQ [63:0]
DM [7:0]
VDD, GND
DQS [7:0]
/DQS [7:0]
/EVENT
SA [1:0]
SDA
I/O
IN
Supply
I/O
I/O
Out
IN
I/O
-
Active High
-
Positive Edge
Negative Edge
-
-
-
SCL
IN
-
VDDSPD
Supply
-
Viking Technology2950
Red Hill Ave
Costa Mesa, CA 92626
Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com
This Data Sheet is subject to change without notice.
Doc. # PS5DUxxxx18xxxyzT
Revision A
Created By: Brian Ouellette
Page 3 of 16
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