PT7V4050GACHA18.432/17.664 datasheet, PDF

PT7V4050GACHA18.432/17.664: DescriptionPLL/Frequency Synthesis Circuit,; CategoryAnalog mixed-signal IC The signal circuit; File Size156KB，7 Pages; ManufacturerDiodes Incorporated

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PT7V4050GACHA18.432/17.664 Overview

PLL/Frequency Synthesis Circuit,

Parameter Name	Attribute value
Objectid	4000532310
package instruction	PACKAGE-16
Reach Compliance Code	compliant
ECCN code	EAR99
Analog Integrated Circuits - Other Types	PHASE DETECTOR
JESD-30 code	R-PDSO-N16
length	20.32 mm
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Maximum seat height	4.15 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	2.54 mm
Terminal location	DUAL
width	10.16 mm

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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