EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

D10BU390J5SB

Description
Ceramic Capacitor, Ceramic, 50V, 5% +Tol, 5% -Tol, BU, 0.000039uF, 0101,
CategoryPassive components    capacitor   
File Size217KB,4 Pages
ManufacturerKnowles
Websitehttp://www.knowles.com
Environmental Compliance
Download Datasheet Parametric View All

D10BU390J5SB Overview

Ceramic Capacitor, Ceramic, 50V, 5% +Tol, 5% -Tol, BU, 0.000039uF, 0101,

D10BU390J5SB Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid865910664
package instruction, 0101
Reach Compliance Codecompliant
ECCN codeEAR99
capacitance0.000039 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
high0.102 mm
length0.254 mm
negative tolerance5%
Number of terminals2
Maximum operating temperature85 °C
Minimum operating temperature10 °C
Package formAxial
method of packingWaffle Pack
positive tolerance5%
Rated (DC) voltage (URdc)50 V
seriesDI-CAP(OTHER)
size code0101
Temperature characteristic codeBU
width0.254 mm
Research on A-type digital flaw detection system based on FPGA.pdf
Research on A-type digital flaw detection system based on FPGA.pdf...
zxopenljx EE_FPGA Learning Park
Phase loss detection of three-phase three-wire circuit
[i=s] This post was last edited by New Electrician Seeking Guidance on 2020-4-1 14:10[/i]I am going to make a soft start switch for a three-phase circuit recently, which needs to realize the phase los...
电工新手求指导 Analog electronics
What is the packaging of integrated circuits? What are the common types of packaging? What are their respective characteristics?
[b][font=宋体][size=4] [/size][/font][/b][b][font=宋体][size=5][color=#0000ff]1. What is the package of integrated circuits? [/color][/size][/font][/b][font=宋体][size=4] [/size][/font] [align=left][color=r...
tiankai001 PCB Design
Vivado prompts [Synth 8-91] ambiguous clock in event control Problem Cause
Comprehensive prompt [Synth 8-91] ambiguous clock in event control. Later it was found that the reason was because the if was written in the always and the else was omitted....
littleshrimp FPGA/CPLD
Simulation and Testbench Design.zip
Simulation and Testbench Design.zip...
zxopenljx EE_FPGA Learning Park

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号