T429G686K015DKTLVL7280 datasheet, PDF

T429G686K015DKTLVL7280: DescriptionTantalum Capacitor, Polarized, Tantalum (dry/solid), 15V, 10% +Tol, 10% -Tol, 68uF, 2711,; CategoryPassive components capacitor; File Size2MB，20 Pages; ManufacturerKEMET; Websitehttp://www.kemet.com

Download Datasheet Parametric View All

T429G686K015DKTLVL7280 Overview

Tantalum Capacitor, Polarized, Tantalum (dry/solid), 15V, 10% +Tol, 10% -Tol, 68uF, 2711,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	7058704563
package instruction	, 2711
Reach Compliance Code	not_compliant
ECCN code	EAR99
capacitance	68 µF
Capacitor type	TANTALUM CAPACITOR
dielectric materials	TANTALUM (DRY/SOLID)
ESR	300 mΩ
high	2.79 mm
JESD-609 code	e0
length	6.73 mm
Manufacturer's serial number	T429
negative tolerance	10%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package form	SMT
method of packing	TR, Plastic, 13 Inch
polarity	POLARIZED
positive tolerance	10%
Rated (DC) voltage (URdc)	15 V
Guideline	MIL-PRF-55365/11
series	T429
size code	2711
Terminal surface	Tin/Lead (Sn90Pb10)
width	2.79 mm

About USB2.0 plug-in and switch: Can I use a high-speed analog switch such as TS3USB31 to switch DM/DP? According to the 3.0 protocol, the complete insertion/removal process needs to detect the VBus timing, and if only the data line ...; Ejack1979 Integrated technical exchanges

[Atria AT32WB415 Series Bluetooth BLE 5.0 MCU] + Bluetooth communication: [Atria AT32WB415 Series Bluetooth BLE 5.0 MCU] + Bluetooth communicationBluetooth BLE Application NotesAfter checking the official website, I found the Bluetooth manual and started to learn and unders...; 雨夜很凉快 RF/Wirelessly

xilinx vivado xdc constraint syntax: 1. Purpose of Constraints Introduce the principle of FPGA constraints, understand that the purpose of constraints is to serve the design, to ensure that the design meets the timing requirements, and t...; zxopenljx EE_FPGA Learning Park

Design and Implementation of Digital Video Conversion Interface Based on FPGA: ...; 至芯科技FPGA大牛 FPGA/CPLD

[AT-START-F403A Evaluation] VI. FreeRTOS system based on IAR security library (sLib) secondary development mode practice: [i=s]This post was last edited by uuxz99 on 2020-10-22 21:47[/i]In the process of implementing the slib function in the previous evaluation, due to the IAR crash problem, a compromise method was used ...; uuxz99 Domestic Chip Exchange

Function parameter definition generated by Microchip Harmony: Using the IO port setting function generated by Microchip Harmony, how to give the value of the following mask parameter? ? Set the digital IO port to 1 void SYS_PORTS_Set( PORTS_MODULE_ID index, PORT...; rayhui100 Microchip MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components